# US 10,770,562 B1 · Interlayer dielectric replacement techniques with protection for source/drain contacts

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- Number: US 10,770,562 B1
- Document ID: US10770562B1
- Status: Granted
- Kind: B1
- Application number: 16/290,182
- Filed: 2019-03-01
- Published: 2020-09-03
- Granted: 2020-09-08
- Earliest claimed: 2019-03-01
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Juntao Li; Andrew Greene; Vimal Kamineni; Adra Carr; Chanro Park; Ruilong Xie
- Web page: https://patentgrep.com/patent/US10770562B1

## CPC

- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3454: {Amorphous}
- H10P 14/414: {of metal-silicide materials}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 50/283: {by chemical means}
- H10P 52/403: {of conductive or resistive materials}
- H10P 95/062: {involving a dielectric removal step}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/066: {by forming silicides of refractory metals}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Techniques are provided for fabricating a semiconductor integrated circuit device which implement an interlayer dielectric (ILD) layer replacement process to replace an initial sacrificial ILD layer with a low-k ILD layer, while forming silicide or dielectric capping layers to protect source/drain contacts of field-effect transistor devices from etch damage during the ILD replacement process. For example, source/drain contact openings (e.g., trenches) are formed in a sacrificial ILD layer and metallic source/drain contacts are formed in the source/drain contact openings. Protective capping layers (e.g., metal-semiconductor alloy capping layers or dielectric capping layers) are formed on upper surfaces of the metallic source/drain contacts. The sacrificial ILD layer is removed using an etch process to etch down the sacrificial ILD layer selective to the protective capping layers, and a low-k ILD layer is formed in place of the removed sacrificial ILD layer.

## Claims

### Claim 1

A method for fabricating a semiconductor IC device, comprising:
forming a field-effect transistor device on a semiconductor substrate, wherein the field-effect transistor device comprises a gate structure and source/drain layers;
forming a sacrificial interlayer dielectric layer to encapsulate the field-effect transistor device;
performing a metallization process to form metallic source/drain contacts in the sacrificial interlayer dielectric layer in contact with source/drain layers of the field-effect transistor device;
depositing a semiconductor layer on the sacrificial interlayer dielectric layer and the metallic source/drain contacts;
performing a thermal anneal process to induce a reaction between the semiconductor layer and the metallic source-drain contacts to form metal-semiconductor alloy capping layers in upper surface regions of the metallic source/drain contacts;
removing unreacted portions of the semiconductor layer remaining after the thermal anneal process;
performing an etch process to remove the sacrificial interlayer dielectric layer, wherein the etch process is selective to the metal-semiconductor alloy capping layers such that the metal-semiconductor alloy capping layers protect the metallic source/drain contacts from etch damage during the etch process; and
forming a low-k interlayer dielectric layer in place of the removed sacrificial interlayer dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the semiconductor layer comprises amorphous silicon.

### Claim 3 (depends on 1)

The method of claim 1, wherein the metallic source/drain contacts comprise one of cobalt and ruthenium.

### Claim 4 (depends on 1)

The method of claim 1, wherein the metal-semiconductor alloy capping layers comprise a cobalt-silicon alloy.

### Claim 5 (depends on 1)

The method of claim 1, wherein the low-k interlayer dielectric layer comprises dielectric material having a dielectric constant k of about 3.0 or less.

### Claim 6 (depends on 1)

The method of claim 1, wherein the sacrificial interlayer dielectric layer comprises silicon oxide.

### Claim 7 (depends on 1)

The method of claim 1, wherein the sacrificial interlayer dielectric layer comprises a first sacrificial interlayer dielectric layer having an upper surface coplanar with an upper surface of the gate structure of the field-effect transistor device, and a second sacrificial interlayer dielectric layer formed on a planarized surface of the first sacrificial interlayer dielectric layer, and where performing the metallization process comprises:
patterning the first and second sacrificial interlayer dielectric layer to form a merged source/drain contact trench that exposes the gate structure and the source/drain layers of the field-effect transistor device; and
filling the merged source/drain contact trench with metallic material to form a merged metallic source/drain contact;
wherein the semiconductor layer is deposited on the second sacrificial interlayer dielectric layer and the merged metallic source/drain contact.

### Claim 8 (depends on 7)

The method of claim 7, wherein forming the low-k interlayer dielectric layer in place of the removed sacrificial interlayer dielectric layer comprises:
depositing a layer of low-k dielectric material to re-fill spaces in which the material of the first sacrificial interlayer dielectric layer was removed and to cover the metal-semiconductor alloy capping layers; and
performing a chemical-mechanical planarizing process to (i) remove overburden portions of the layer of low-k dielectric material, (ii) remove the metal-semiconductor alloy capping layers, and to (iii) remove a portion of the merged metallic source/drain contact above the gate structure to form discrete metallic source drain contacts.

### Claim 9 (depends on 1)

The method of claim 1, wherein performing the metallization process comprises:
patterning the sacrificial interlayer dielectric layer to form discrete contact trenches on opposite sides of the gate structure to expose the source/drain layers of the field-effect transistor device; and
filling the discrete source/drain contact trenches with metallic material to form discrete metallic source/drain contacts.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming the low-k interlayer dielectric layer in place of the removed sacrificial interlayer dielectric layer comprises:
depositing a layer of low-k dielectric material to re-fill spaces in which the material of the sacrificial interlayer dielectric layer was removed and to cover the metal-semiconductor alloy capping layers; and
performing a chemical-mechanical planarizing process to remove overburden portions of the layer of low-k dielectric material and expose the metal-semiconductor alloy capping layers.

### Claim 11 (depends on 10)

The method of claim 10, further comprising forming metallic vias in contact with the metal-semiconductor alloy capping layers of metallic source/drain contacts.

### Claim 12 (depends on 9)

The method of claim 9, wherein forming the low-k interlayer dielectric layer in place of the removed sacrificial interlayer dielectric layer comprises:
depositing a layer of low-k dielectric material to re-fill spaces in which the material of the sacrificial interlayer dielectric layer was removed and to cover the metal-semiconductor alloy capping layers; and
performing a chemical-mechanical planarizing process to (i) remove overburden portions of the layer of low-k dielectric material and to (ii) remove the metal-semiconductor alloy capping layers and expose the metallic source/drain contacts.