# US 10,770,561 B2 · Methods of fabricating dual threshold voltage devices

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- Number: US 10,770,561 B2
- Document ID: US10770561B2
- Status: Granted
- Kind: B2
- Application number: 16/261,414
- Filed: 2019-01-29
- Published: 2019-10-10
- Granted: 2020-09-08
- Earliest claimed: 2018-01-08
- Assignees: Spin Memory, Inc.
- Applicants: Spin Memory, Inc.
- Inventors: Gian Sharma; Amitay Levi; Kuk-Hwan Kim
- Web page: https://patentgrep.com/patent/US10770561B2

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6728: {Vertical TFTs}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 64/031: {of data-storage electrodes}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10P 14/414: {of metal-silicide materials}
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

An annular device is provided. The annular device includes a first transistor including a first input terminal and a second transistor including a second input terminal. The first input terminal and the second input terminal extend radially outward from the annular device, and wherein the first input terminal is aligned with the second input terminal.

## Claims

### Claim 1

An annular device, comprising:
a cylindrical pillar, comprising:
a vertical cylindrical core; and
a plurality of layers that surround the vertical cylindrical core in succession, the plurality of layers including a first layer, a second layer, a third layer, and a fourth layer,
wherein:
the core, the first layer, and the second layer correspond to a first transistor including a first input terminal, wherein the first transistor is configured to have a first threshold voltage having a first magnitude; and
the second layer, the third layer, and the fourth layer correspond to a second transistor including a second input terminal, wherein the second transistor is configured to have a second threshold voltage having a second magnitude distinct from the first magnitude.

### Claim 2 (depends on 1)

The annular device of claim 1, wherein:
the second layer is a common channel having a channel source and a channel drain;
the first input terminal is coupled to the core, the first input terminal being configured to receive a first voltage for the first transistor; and
the second input terminal is coupled to the fourth layer, the second input terminal being configured to receive a second voltage for the second transistor.

### Claim 3 (depends on 2)

The annular device of claim 2, further comprising a magnetic tunnel junction (MTJ) coupled to the channel drain.

### Claim 4 (depends on 2)

The annular device of claim 2, further comprising a cylindrical source contact coupled to the channel source.

### Claim 5 (depends on 3)

The annular device of claim 3, wherein:
the MTJ includes a storage layer, a spacer layer, and a reference layer; and
the reference layer of the MTJ is coupled to the channel drain.

### Claim 6 (depends on 1)

The annular device of claim 1, wherein:
the first layer is a first dielectric layer;
the third layer is a third dielectric layer; and
the first threshold voltage and the second threshold voltage are based on respective thicknesses for the first dielectric layer and the third dielectric layer.

### Claim 7 (depends on 1)

The annular device of claim 1, wherein the first threshold voltage and the second threshold voltage are selected by changing one or more properties of the annular device selected from the group consisting of: a dopant of the annular device, a material composition of the first input terminal, a work function of the first input terminal, a material composition of the second input terminal, and a work function of the second input terminal.

### Claim 8 (depends on 1)

The annular device of claim 1, wherein:
the core is conductive;
the first layer is a first dielectric layer that surrounds the core;
the second layer surrounds the first dielectric layer and is composed of a semiconductor material;
the third layer is a third dielectric layer that surrounds the second layer; and
the fourth layer is conductive and surrounds the third dielectric layer.

### Claim 9 (depends on 1)

The annular device of claim 1, wherein the fourth layer is composed of a polycide.

### Claim 10 (depends on 1)

The annular device of claim 1, wherein the core is composed of a Tantalum material.

### Claim 11 (depends on 1)

The annular device of claim 1, wherein the second layer has a height that is distinct from a height of the core.

### Claim 12 (depends on 1)

The annular device of claim 1, wherein the second layer has a height that is distinct from a respective height of the third layer and the fourth layer.

### Claim 13 (depends on 1)

The annular device of claim 1, wherein the first input terminal and the second input terminal extend radially outward from the annular device.

### Claim 14 (depends on 1)

The annular device of claim 1, wherein the first input terminal is aligned with the second input terminal.

### Claim 15

An annular device, comprising:
a core; and
a plurality of layers that surround the core in succession, the plurality of layers including a first layer, a second layer, a third layer, and a fourth layer, wherein:
the core, the first layer, and the second layer correspond to a first transistor including having a first input terminal; and
the second layer, the third layer, and the fourth layer correspond to a second transistor including having a second input terminal; and
the second layer is a common channel having a channel source and a channel drain;
the first input terminal is coupled to the core, the first input terminal being configured to receive a first voltage for the first transistor; and
the second input terminal is coupled to the fourth layer, the second input terminal being configured to receive a second voltage for the second transistor.