# US 10,770,559 B2 · Gate structure and methods of forming metal gate isolation

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- Number: US 10,770,559 B2
- Document ID: US10770559B2
- Status: Granted
- Kind: B2
- Application number: 16/397,224
- Filed: 2019-04-29
- Published: 2019-10-31
- Granted: 2020-09-08
- Earliest claimed: 2018-04-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chun-Sheng Liang; Meng-Fang Hsu
- Web page: https://patentgrep.com/patent/US10770559B2

## CPC

- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming high-k metal gates (HKMGs) includes removing a dummy gate structure formed over a first fin and a second fin to form a trench that exposes portions of the first fin and the second fin, forming a high-k dielectric layer over the exposed portions of the first fin and the second fin, forming a capping layer over the high-k dielectric layer, forming a hard mask layer over the capping layer, such that the hard mask layer fills the trench completely, forming an isolation feature in the hard mask layer between the first fin and the second fin, the isolation feature having sidewalls that extend through the capping layer, removing the hard mask layer to expose the capping layer and the sidewalls of the isolation feature, and forming a conductive electrode over the capping layer and along the sidewalls of the isolation feature.

## Claims

### Claim 1

A method, comprising:
removing a dummy gate structure disposed over a first fin and a second fin to form a gate trench;
forming a high-k dielectric layer in the gate trench;
forming a hard mask layer over the high-k dielectric layer to fill the gate trench;
forming an isolation feature in the hard mask layer between the first fin and the second fin, the isolation feature having sidewalls that extend through a bottom surface of the hard mask layer;
removing the hard mask layer to expose the sidewalls of the isolation feature;
forming a work function metal layer over the high-k dielectric layer, such that the work function metal layer is formed over the sidewalls and a top surface of the isolation feature;
forming a bulk conductive layer over the work function metal layer; and
removing a portion of the work function metal layer formed over the top surface of the isolation feature, such that a top surface of the work function metal layer is substantially coplanar with the top surface of the isolation feature.

### Claim 2 (depends on 1)

The method of claim 1, wherein removing the portion of the work function metal layer includes performing a chemical-mechanical polishing (CMP) process to the work function metal layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the isolation feature includes:
forming an opening in the hard mask layer between the first fin and the second fin;
filling the opening with an insulating material; and
performing a chemical-mechanical polishing (CMP) to planarize a top surface of the hard mask layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein bottom portions of the first fin and the second fin are separated by an isolation structure, and wherein forming the opening removes a portion of the isolation structure.

### Claim 5 (depends on 1)

The method of claim 1, further comprising forming a capping layer over the high-k dielectric layer before forming the work function metal layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein removing the hard mask layer includes performing a first dry etching process using a first etchant that includes O2, CHF3, CH3F, Cl2, or combinations thereof, and subsequently performing a second dry etching process using a second etchant that includes NF3, H2, or a combination thereof.

### Claim 7 (depends on 1)

The method of claim 1, wherein removing the hard mask layer includes performing a dry etching process using a first etchant that includes O2, CHF3, CH3F, Cl2, or combinations thereof, and subsequently performing a wet etching process using a second etchant that includes sulfuric acid, hydrogen peroxide, or a combination thereof.

### Claim 8

A method, comprising:
providing a semiconductor structure that includes:
a first fin and a second fin formed over a substrate, bottom portions of the first fin and the second fin being separated by an isolation structure; and
a dummy gate structure formed over a channel region of the first fin and the second fin;
removing the dummy gate structure to form a trench exposing the first fin and the second fin;
depositing a high-k dielectric layer in the trench;
depositing a hard mask layer over the high-k dielectric layer;
forming an opening in the hard mask layer between the first fin and the second fin;
forming a dielectric feature in the opening;
removing the hard mask layer to expose the trench;
depositing a work function metal layer in the trench such that a portion of the work function metal layer is deposited on a sidewall of the dielectric feature; and
forming a bulk conductive layer over the work function metal layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein forming the opening in the hard mask layer exposes the high-k dielectric layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming the opening includes performing a first dry etching process using a first etchant that includes O2, CHF3, CH3F, Cl2, or combinations thereof, and subsequently performing a second dry etching process using a second etchant that includes NF3, H2, or a combination thereof.

### Claim 11 (depends on 8)

The method of claim 8, wherein forming the opening removes a portion of the isolation structure.

### Claim 12 (depends on 11)

The method of claim 11, wherein forming the opening includes performing a dry etching process using a first etchant that includes O2, CHF3, CH3F, Cl2, or combinations thereof, and subsequently performing a wet etching process using a second etchant that includes sulfuric acid, hydrogen peroxide, or a combination thereof.

### Claim 13 (depends on 8)

The method of claim 8, further comprising forming a barrier layer in the trench after removing the hard mask layer and before depositing the work function metal layer.

### Claim 14 (depends on 8)

The method of claim 8, wherein forming the hard mask layer includes depositing silicon over the high-k dielectric layer.

### Claim 15 (depends on 8)

The method of claim 8, wherein forming the hard mask layer includes depositing an oxide-based material over the high-k dielectric layer.

### Claim 16

A semiconductor structure, comprising:
a fin protruding from a substrate;
a high-k metal gate (HKMG) disposed over the fin, wherein a first portion of the HKMG includes a high-k dielectric layer disposed over the fin, a work function metal layer disposed over the high-k dielectric layer, and a bulk conductive layer disposed over the work function metal layer, and wherein a top surface of the work function metal layer is substantially coplanar with a top surface of the bulk conductive layer; and
a dielectric feature disposed over the substrate and adjacent to the HKMG, wherein a second portion of the HKMG includes the work function metal layer disposed vertically along a sidewall of the dielectric feature and the bulk conductive layer disposed over the work function metal layer.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, wherein a bottom surface of the dielectric feature is defined by the high-k dielectric layer.

### Claim 18 (depends on 16)

The semiconductor structure of claim 16, further comprising an isolation structure disposed over the substrate, wherein a top surface of the isolation structure is below a top surface of the fin, and wherein a bottom surface of the dielectric feature is below the top surface of the isolation structure.

### Claim 19 (depends on 16)

The semiconductor structure of claim 16, wherein the HKMG further includes a barrier layer interposing between the work function metal layer and the high-k dielectric layer.

### Claim 20 (depends on 16)

The semiconductor structure of claim 16, wherein the top surface of the work function metal layer is substantially planar with a top surface of the dielectric feature.