# US 10,770,557 B2 · Tunable breakdown voltage RF FET devices

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- Number: US 10,770,557 B2
- Document ID: US10770557B2
- Status: Granted
- Kind: B2
- Application number: 15/982,370
- Filed: 2018-05-17
- Published: 2018-09-20
- Granted: 2020-09-08
- Earliest claimed: 2014-06-10
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Vibhor Jain; Qizhi Liu; John J. Pekarik
- Web page: https://patentgrep.com/patent/US10770557B2

## CPC

- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/061: {of FETs having Schottky gates (H10D30/015 takes precedence)}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/87: FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET] {(FETs having Schottky contact on top of heterojunction gate H10D30/801)}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/0131: {the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 30/0614: {using processes wherein the final gate is made after the completion of the source and drain regions, e.g. gate-last processes using dummy gates}
- H10D 64/64: Electrodes comprising a Schottky barrier to a semiconductor
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

## Claims

### Claim 1

A method, comprising:
forming a first line and a second line on an underlying gate dielectric material on an underlying substrate, the second line having a width tuned to a breakdown voltage, the first line and the underlying gate dielectric material forming a gate structure;
depositing sidewall material on the first line, the second line and on an upper surface of the underlying gate dielectric material including between the first line and the second line;
forming tapered sidewall spacers on sidewalls of the first line and the second line, and forming non-tapered sidewall spacers opposing the tapered sidewall spacers on opposing sides of the first line and second line by removing the sidewall material on horizontal surfaces of the first line, the second line and portions of the upper surface of the underlying gate dielectric material;
forming source and drain regions adjacent to the outer edges of the first line and the second line by an implantation process through the underlying gate dielectric material adjacent to the non-tapered sidewall spacers;
removing the second line to form an opening between a tapered sidewall spacer of the second line a non-tapered sidewall spacer of the second line, to expose the underlying gate dielectric material;
blanket depositing a blocking material on the exposed underlying gate dielectric material within the opening and over the source and drain regions, and over the tapered sidewall spacers and the non-tapered sidewall spacers, wherein the blocking material fills in the taper of the tapered sidewall spacers;
removing the blocking material and the dielectric material from over the source and drain regions by removal of the first line between a tapered sidewall spacer of the first line and a non-tapered sidewall spacer of the first line, while leaving the blocking material and the dielectric material within the second opening between a tapered sidewall spacer of the second line and a non-tapered sidewall spacer of the second line; and
forming a silicide on the first line;
forming silicide regions in contact with the source and drain regions; and
forming contacts to the gate structure and the source and drain regions.

### Claim 2 (depends on 1)

The method of claim 1, further comprising adjusting the width of the second line to control a dimension of the second opening to tune the breakdown voltage.

### Claim 3 (depends on 1)

The method of claim 1, wherein the forming of the first line and the second line comprises a blanket deposition of semiconductor followed by a patterning process.

### Claim 4 (depends on 1)

The method of claim 1, wherein the silicide regions are formed on the source and drain regions, prior to forming the contacts.

### Claim 5 (depends on 1)

The method of claim 1, wherein the source region is formed remotely from the gate structure.

### Claim 6 (depends on 1)

The method of claim 1, wherein the blocking material is a deposited dielectric material.

### Claim 7 (depends on 6)

The method of claim 6, wherein the tapered sidewall spacers are deposited between the first line and the second line and define a minimum spacing between the first line and the second line.

### Claim 8 (depends on 7)

The method of claim 7, wherein the depositing of the sidewall material pinches off the minimum spacing.

### Claim 9 (depends on 1)

The method of claim 1, wherein the source and drain regions are self aligned.

### Claim 10 (depends on 8)

The method of claim 8, wherein the silicide is formed on the first line above the tapered sidewall spacers.

### Claim 11 (depends on 10)

The method of claim 10, wherein the silicide is formed on the first line above the non-tapered sidewall spacers.

### Claim 12 (depends on 11)

The method of claim 11, wherein the tapered sidewall spacers are formed adjacent to each other.

### Claim 13 (depends on 11)

The method of claim 11, wherein the non-tapered sidewall spacers are formed adjacent to the outer edges of the first line and the second line.

### Claim 14 (depends on 13)

The method of claim 13, wherein the non-tapered sidewall spacers are formed adjacent to the source and drain regions.