# US 10,770,549 B2 · Semiconductor device, inverter circuit, driving device, vehicle, and elevator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,549 B2 - Document ID: US10770549B2 - Status: Granted - Kind: B2 - Application number: 16/286,644 - Filed: 2019-02-27 - Published: 2020-01-30 - Granted: 2020-09-08 - Earliest claimed: 2018-07-26 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Toshiyuki Oshima; Shinya Kyogoku; Ryosuke Iijima; Tatsuo Shimizu - Web page: https://patentgrep.com/patent/US10770549B2 ## CPC - H02M 7/003: {Constructional details, e.g. physical layout, assembly, wiring or busbar connections} - H10D 62/8325: {Silicon carbide} - H02M 7/48: using discharge tubes with control electrode or semiconductor devices with control electrode - H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs} - H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes} - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 48/01: Manufacture or treatment - H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 62/157: {Impurity concentrations or distributions} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - B60L 2210/40: DC to AC converters - B66B 1/28: electrical (detecting excessive speed B66B5/04 {; control of electrical motor H02P}) - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B60L: PROPULSION OF ELECTRICALLY-PROPELLED VEHICLES (arrangements or mounting of electrical propulsion units or of plural diverse prime-movers for mutual or common propulsion in vehicles B60K1/00, B60K6/20; arrangements or mounting of electrical gearing in vehicles B60K17/12, B60K17/14; preventing wheel slip by reducing power in rail vehicles B61C15/08; dynamo-electric machines H02K; control or regulation of electric motors H02P); SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES (electric coupling devices combined with mechanical couplings of vehicles B60D1/64; electric heating for vehicles B60H1/00); ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL (control or regulation of electric motors H02P); MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES - B66B: ELEVATORS; ESCALATORS OR MOVING WALKWAYS ({apparatus for raising or lowering persons on theatrical stages or the like A63J5/12} ; funicular railbound systems with rigid ground-supported tracks and cable traction, e.g. cliff railways, B61B9/00; arrangements of ammunition handlers in vessels B63G3/00; hoists, lifts, or conveyors for loading or unloading in general B65G; braking or detent devices controlling normal movements of winding drums or barrels B66D; ship-lifting devices E02C; garages for many vehicles with mechanical means for lifting vehicles E04H6/12; hoists for feeding ammunition or projectiles to launching apparatus or to loading mechanisms F41A9/00) ## Abstract A semiconductor device according to an embodiment includes a silicon carbide layer having a first and second plane, first and second trench extending in first direction, and in the silicon carbide layer, n-type first region, p-type second region between the n-type first region and the first plane and between the first and second trench, p-type fifth region covering bottom of the first trench, p-type sixth region covering bottom of the second trench, n-type seventh region between the fifth region and the second region, n-type eighth region between the sixth and second regions, p-type ninth regions contacting the fifth and second regions, and p-type tenth regions contacting the sixth region and the second region, the ninth and tenth regions repeatedly disposed in the first direction, and a line segment connecting the ninth region and the tenth region is oblique with respect to second direction perpendicular to the first direction. ## Claims ### Claim 1 A semiconductor device comprising: a silicon carbide layer having a first plane and a second plane facing the first plane, the first plane and the second plane being parallel to a first direction and a second direction perpendicular to the first direction; a first trench provided in the silicon carbide layer, the first trench extending in the first direction on the first plane, and the first trench having a first side plane, a second side plane, and a first bottom plane between the first side plane and the second side plane; a first gate electrode located in the first trench; a first gate insulating layer located between the first gate electrode and the silicon carbide layer; a second trench provided in the silicon carbide layer, the second trench extending in the first direction on the first plane, and the second trench having a third side plane facing the second side plane, a fourth side plane, and a second bottom plane between the third side plane and the fourth side plane; a second gate electrode located in the second trench; a second gate insulating layer located between the second gate electrode and the silicon carbide layer; a first silicon carbide region of n-type located in the silicon carbide layer; a second silicon carbide region of p-type located in the silicon carbide layer, the second silicon carbide region being located between the first silicon carbide region and the first plane, and the second silicon carbide region being located between the first trench and the second trench; a third silicon carbide region of n-type located in the silicon carbide layer and located between the second silicon carbide region and the first plane; a fourth silicon carbide region of n-type located in the silicon carbide layer and located between the second silicon carbide region and the first plane, the third silicon carbide region being interposed between the first trench and the fourth silicon carbide region; a fifth silicon carbide region of p-type located in the silicon carbide layer and located between the first silicon carbide region and the first trench, the fifth silicon carbide region covering the first bottom plane; a sixth silicon carbide region of p-type located in the silicon carbide layer and located between the first silicon carbide region and the second trench, the sixth silicon carbide region covering the second bottom plane, and the first silicon carbide region being interposed between the fifth silicon carbide region and the sixth silicon carbide region; a seventh silicon carbide region of n-type located in the silicon carbide layer and located between the fifth silicon carbide region and the second silicon carbide region; an eighth silicon carbide region of n-type located in the silicon carbide layer and located between the sixth silicon carbide region and the second silicon carbide region; a plurality of ninth silicon carbide regions of p-type located in the silicon carbide layer and located between the fifth silicon carbide region and the second silicon carbide region, the ninth silicon carbide regions being in contact with the fifth silicon carbide region and the second silicon carbide region, and the ninth silicon carbide regions being repeatedly disposed in the first direction; and a plurality of tenth silicon carbide regions of p-type located in the silicon carbide layer and located between the sixth silicon carbide region and the second silicon carbide region, the tenth silicon carbide regions being in contact with the sixth silicon carbide region and the second silicon carbide region, and the tenth silicon carbide regions being repeatedly disposed in the first direction, wherein a virtual line segment connecting the ninth silicon carbide region and the tenth silicon carbide region and being parallel to the first plane is oblique with respect to the second direction. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the seventh silicon carbide region and the eighth silicon carbide region are in contact between the first trench and the second trench. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein an n-type impurity concentration of the seventh silicon carbide region and an n-type impurity concentration of the eighth silicon carbide region are higher than an n-type impurity concentration of the first silicon carbide region. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the ninth silicon carbide regions and the tenth silicon carbide regions are alternately disposed in the first direction. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein a first pitch of disposition of the ninth silicon carbide regions is constant, a second pitch of disposition of the tenth silicon carbide regions is constant, and the first pitch and the second pitch are substantially equal. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein a p-type impurity concentration of the ninth silicon carbide region and a p-type impurity concentration of the tenth silicon carbide region are higher than a p-type impurity concentration of the second silicon carbide region. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the ninth silicon carbide region is in contact with the second side plane and the tenth silicon carbide region is in contact with the third side plane. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the seventh silicon carbide region is interposed between the ninth silicon carbide region and the second side plane and the eighth silicon carbide region is interposed between the tenth silicon carbide region and the third side plane. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, further comprising: an eleventh silicon carbide region of p-type located in the silicon carbide layer and located between the first silicon carbide region and the first plane, the first trench being interposed between the second silicon carbide region and the eleventh silicon carbide region; a twelfth silicon carbide region of n-type located in the silicon carbide layer and located between the eleventh silicon carbide region and the first plane; a thirteenth silicon carbide region of n-type located in the silicon carbide layer and located between the fifth silicon carbide region and the eleventh silicon carbide region; and a plurality of fourteenth silicon carbide regions of p-type located in the silicon carbide layer and located between the fifth silicon carbide region and the eleventh silicon carbide region, the fourteenth silicon carbide regions being in contact with the fifth silicon carbide region and the eleventh silicon carbide region, and the fourteenth silicon carbide regions being repeatedly disposed in the first direction. ### Claim 10 (depends on 9) The semiconductor device according to claim 9, wherein a virtual line segment connecting the ninth silicon carbide region and the fourteenth silicon carbide region and being parallel to the first plane is oblique with respect to the second direction. ### Claim 11 (depends on 9) The semiconductor device according to claim 9, wherein a virtual line segment connecting the ninth silicon carbide region and the fourteenth silicon carbide region and being parallel to the first plane is parallel to the second direction. ### Claim 12 (depends on 9) The semiconductor device according to claim 9, further comprising: a fifteenth silicon carbide region of p-type located in the silicon carbide layer and located between the first silicon carbide region and the first plane, the second trench being interposed between the second silicon carbide region and the fifteenth silicon carbide region; a sixteenth silicon carbide region of n-type located in the silicon carbide layer and located between the fifteenth silicon carbide region and the first plane; a seventeenth silicon carbide region of n-type located in the silicon carbide layer and located between the sixth silicon carbide region and the fifteenth silicon carbide region; and a plurality of eighteenth silicon carbide regions of p-type located in the silicon carbide layer and located between the sixth silicon carbide region and the fifteenth silicon carbide region, the eighteenth silicon carbide regions being in contact with the sixth silicon carbide region and the fifteenth silicon carbide region, and the fifteenth silicon carbide region being repeatedly disposed in the first direction. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein a virtual line segment connecting the tenth silicon carbide region and the eighteenth silicon carbide region and being parallel to the first plane is oblique with respect to the second direction. ### Claim 14 (depends on 12) The semiconductor device according to claim 12, wherein a virtual line segment connecting the tenth silicon carbide region and the eighteenth silicon carbide region and being parallel to the first plane is parallel to the second direction. ### Claim 15 (depends on 1) An inverter circuit comprising a semiconductor device according to claim 1. ### Claim 16 (depends on 1) A driving device comprising a semiconductor device according to claim 1. ### Claim 17 (depends on 1) A vehicle comprising a semiconductor device according to claim 1. ### Claim 18 (depends on 1) An elevator comprising a semiconductor device according to claim 1. ### Claim 19 A semiconductor device comprising: a silicon carbide layer having a first plane and a second plane facing the first plane, the first plane and the second plane being parallel to a first direction and a second direction perpendicular to the first direction; a first trench provided in the silicon carbide layer, the first trench extending in the first direction on the first plane, and the first trench having a first side plane, a second side plane, and a first bottom plane between the first side plane and the second side plane; a first gate electrode located in the first trench; a first gate insulating layer located between the first gate electrode and the silicon carbide layer; a second trench provided in the silicon carbide layer, the second trench extending in the first direction on the first plane, and the second trench having a third side plane facing the second side plane, a fourth side plane, and a second bottom plane between the third side plane and the fourth side plane; a second gate electrode located in the second trench; a second gate insulating layer located between the second gate electrode and the silicon carbide layer; a first silicon carbide region of n-type located in the silicon carbide layer; a second silicon carbide region of p-type located in the silicon carbide layer, the second silicon carbide region being located between the first silicon carbide region and the first plane, and the second silicon carbide region being located between the first trench and the second trench; a third silicon carbide region of n-type located in the silicon carbide layer and located between the second silicon carbide region and the first plane; a fourth silicon carbide region of n-type located in the silicon carbide layer and located between the second silicon carbide region and the first plane, the third silicon carbide region being interposed between the first trench and the fourth silicon carbide region; a fifth silicon carbide region of p-type located in the silicon carbide layer and located between the first silicon carbide region and the first trench, the fifth silicon carbide region covering the first bottom plane; a sixth silicon carbide region of p-type located in the silicon carbide layer and located between the first silicon carbide region and the second trench, the sixth silicon carbide region covering the second bottom plane, and the first silicon carbide region being interposed between the fifth silicon carbide region and the sixth silicon carbide region; a seventh silicon carbide region of n-type located in the silicon carbide layer and located between the fifth silicon carbide region and the second silicon carbide region; an eighth silicon carbide region of n-type located in the silicon carbide layer and located between the sixth silicon carbide region and the second silicon carbide region; a plurality of ninth silicon carbide regions of p-type located in the silicon carbide layer and located between the fifth silicon carbide region and the second silicon carbide region, the ninth silicon carbide regions being in contact with the fifth silicon carbide region and the second silicon carbide region, and the ninth silicon carbide regions being repeatedly disposed in the first direction; and a plurality of tenth silicon carbide regions of p-type located in the silicon carbide layer and located between the sixth silicon carbide region and the second silicon carbide region, the tenth silicon carbide regions being in contact with the sixth silicon carbide region and the second silicon carbide region, and tenth silicon carbide regions being repeatedly disposed in the first direction, wherein the seventh silicon carbide region is interposed between the ninth silicon carbide region and the second side plane and the eighth silicon carbide region is interposed between the tenth silicon carbide region and the third side plane. ### Claim 20 (depends on 19) The semiconductor device according to claim 19, wherein the seventh silicon carbide region and the eighth silicon carbide region are connected between the first trench and the second trench.