# US 10,770,547 B2 · Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses

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- Number: US 10,770,547 B2
- Document ID: US10770547B2
- Status: Granted
- Kind: B2
- Application number: 16/657,409
- Filed: 2019-10-18
- Published: 2020-02-13
- Granted: 2020-09-08
- Earliest claimed: 2014-02-28
- Assignees: STMicroelectronics (Rousset) SAS
- Applicants: STMicroelectronics (Rousset) SAS
- Inventors: Guilhem Bouton; Pascal Fornara; Christian Rivero
- Web page: https://patentgrep.com/patent/US10770547B2

## CPC

- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10B 20/65: {of memory structures of the ROM only type}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/795: {being in lateral device isolation regions, e.g. STI}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/041: {of isolation regions comprising polycrystalline semiconductor materials}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/40: Isolation regions comprising polycrystalline semiconductor materials
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

## Claims

### Claim 1

A circuit, comprising:
a semiconductor substrate;
an insulating region delimiting an active region of the semiconductor substrate;
at least one component unfavorably sensitive to compressive stress at least partially in the active region, wherein the at least one component unfavorably sensitive to compressive stress is an NMOS transistor belonging to a control unit of a memory plane of an integrated memory device, the memory plane having nonvolatile memory cells and selection transistors with buried gates formed in trenches;
at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region;
wherein the at least one electrically inactive trench and the trenches for the buried gates have a same depth within the semiconductor substrate.

### Claim 2 (depends on 1)

The circuit according to claim 1, further comprising:
an additional insulating region comprising an insulating lower layer in compression located above the at least one component unfavorably sensitive to compressive stress, the active region and the insulating region; and
at least one contact region arranged above at least a part of the electrically inactive trench and below the insulating lower layer in compression;
wherein the at least one contact region has a same structure as contacts on source, drain and gate regions of transistors of the memory device.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein an insulated conductor of said electrically inactive trench is not electrically connected to an electrical potential.

### Claim 4

A circuit, comprising:
a semiconductor substrate;
a selection transistor for a memory circuit supported by said semiconductor substrate, wherein the selection transistor comprises:
a first trench in the semiconductor substrate;
an insulated conductor in said first trench to form a buried gate for the selection transistor;
a control circuit for the memory circuit, comprising:
an insulating region in the semiconductor substrate which surrounds an active region;
a circuit component located at least partially in the active region, wherein the circuit component is unfavorably sensitive to compressive stress;
a second trench in the insulating region; and
an insulated conductor in said second trench to form an electrically inactive trench which reduces compressive stress in the active region.

### Claim 5 (depends on 4)

The circuit of claim 4, wherein the circuit component is an NMOS transistor.

### Claim 6 (depends on 4)

The circuit of claim 4, where the insulated conductor of said electrically inactive trench is not electrically connected to an electrical potential.

### Claim 7 (depends on 4)

The circuit of claim 4, further comprising:
an insulating layer in compression, wherein the insulating layer is located above the circuit component that is unfavorably sensitive to compressive stress, the active region and the insulating region; and
at least one contact region arranged above at least a part of the electrically inactive trench and below the insulating lower layer in compression;
wherein the at least one contact region has a same structure as contacts on source, drain and gate regions of transistors of the memory circuit.

### Claim 8 (depends on 4)

The circuit of claim 4, wherein the second trench for the electrically inactive trench and the first trenches for the buried gates have a same depth within the semiconductor substrate.