# US 10,770,546 B2 · High density nanotubes and nanotube devices

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- Number: US 10,770,546 B2
- Document ID: US10770546B2
- Status: Granted
- Kind: B2
- Application number: 16/142,565
- Filed: 2018-09-26
- Published: 2020-03-26
- Granted: 2020-09-08
- Earliest claimed: 2018-09-26
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: ChoongHyun Lee; Kangguo Cheng; Juntao Li; Peng Xu
- Web page: https://patentgrep.com/patent/US10770546B2

## CPC

- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G01N 27/4146: {involving nanosized elements, e.g. nanotubes, nanowires}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/20: of semiconductor materials
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3464: {Nanotubes}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/68: Organic materials, e.g. photoresists
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 50/283: {by chemical means}
- H10P 50/73: {using masks for insulating materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- G01N 27/4145: {specially adapted for biomolecules, e.g. gate electrode with immobilised receptors}
- H10P 14/3802: {Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a semiconductor device includes forming a plurality of pillars on a substrate. Each pillar of the plurality of pillars includes a silicon germanium portion. In the method, a layer of germanium oxide is deposited on the plurality of pillars, and a thermal annealing process is performed to convert outer regions of the silicon germanium portions into a plurality of silicon nanotubes. Each silicon nanotube of the plurality of silicon nanotubes surrounds a silicon germanium core portion. The method also includes exposing top surfaces of each of the silicon germanium core portions, and selectively removing each of the silicon germanium core portions with respect to the plurality of silicon nanotubes to create a plurality of gaps.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising:
forming a plurality of pillars on a substrate, each pillar of the plurality of pillars comprising a silicon germanium portion;
depositing a layer of germanium oxide on the plurality of pillars;
performing a thermal annealing process to convert outer regions of the silicon germanium portions into a plurality of silicon nanotubes, wherein each silicon nanotube of the plurality of silicon nanotubes surrounds a silicon germanium core portion;
exposing top surfaces of each of the silicon germanium core portions; and
selectively removing each of the silicon germanium core portions with respect to the plurality of silicon nanotubes to create a plurality of gaps.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the thermal annealing process is performed in an inert gas ambient.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the thermal annealing process is performed at a temperature of about 800° C. to about 1100° C.

### Claim 4 (depends on 1)

The method according to claim 1, wherein portions of the layer of germanium oxide formed on the silicon germanium portions are converted into silicon oxide by the thermal annealing process.

### Claim 5 (depends on 4)

The method according to claim 4, further comprising removing the silicon oxide and unreacted portions of the germanium oxide layer.

### Claim 6 (depends on 5)

The method according to claim 5, further comprising forming a sacrificial dielectric layer on side surfaces of each of the plurality of silicon nanotubes.

### Claim 7 (depends on 6)

The method according to claim 6, further comprising:
recessing the sacrificial dielectric layer to expose upper portions of the side surfaces of each of the plurality of silicon nanotubes; and
growing source/drain regions from the exposed upper portions of the side surfaces of each of the plurality of silicon nanotubes.

### Claim 8 (depends on 1)

The method according to claim 1, wherein:
a plurality of hardmask layers are respectively formed on the plurality of silicon nanotubes and their corresponding silicon germanium core portions: and
the exposing of the top surfaces of each of the silicon germanium core portions comprises removing the plurality of hardmask layers.

### Claim 9 (depends on 1)

The method according to claim 1, further comprising growing source/drain regions from upper portions of each of the plurality of silicon nanotubes.

### Claim 10 (depends on 9)

The method according to claim 9, wherein the growing is performed until the source/drain regions of each of the plurality of silicon nanotubes are merged with each other.

### Claim 11 (depends on 1)

The method according to claim 1, further comprising depositing a gate structure in each of the plurality of gaps.

### Claim 12 (depends on 11)

The method according to claim 11, further comprising depositing an absorption layer on each of the plurality of silicon nanotubes.

### Claim 13 (depends on 1)

The method according to claim 1, further comprising depositing a dielectric layer in each of the plurality of gaps.

### Claim 14 (depends on 13)

The method according to claim 13, further comprising recessing the dielectric layer to expose an upper portion of each of the plurality of silicon nanotubes.

### Claim 15 (depends on 14)

The method according to claim 14, further comprising growing source/drain regions from upper portions of each of the plurality of silicon nanotubes.

### Claim 16 (depends on 15)

The method according to claim 15, further comprising forming a gate structure around outer surfaces of each of the plurality of silicon nanotubes.

### Claim 17

A method for manufacturing a semiconductor device, comprising:
forming a plurality of semiconductor layers spaced apart from each other on respective pedestal portions of a substrate, each semiconductor layer of the plurality of semiconductor layers comprising germanium;
depositing a layer of germanium oxide on the plurality of semiconductor layers;
performing a thermal annealing process to convert outer regions of the semiconductor layers into a plurality of nanotubes, wherein each nanotube of the plurality of nanotubes surrounds a semiconductor layer core portion;
exposing top surfaces of each of the semiconductor layer core portions; and
selectively removing each of the semiconductor layer core portions with respect to the plurality of nanotubes to create a plurality of gaps.