# US 10,770,545 B2 · Quantum dot devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,545 B2 - Document ID: US10770545B2 - Status: Granted - Kind: B2 - Application number: 16/314,788 - Filed: 2016-08-30 - Published: 2019-07-04 - Granted: 2020-09-08 - Earliest claimed: 2016-08-30 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Hubert C. George; Ravi Pillarisetty; Jeanette M. Roberts; Nicole K. Thomas; James S. Clarke - Web page: https://patentgrep.com/patent/US10770545B2 ## CPC - H10D 62/121: {oriented parallel to substrates} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - B82Y 40/00: Manufacture or treatment of nanostructures - H10D 30/402: {Single electron transistors; Coulomb blockade transistors} - H10D 30/473: {having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT} - H10D 30/751: {having composition variations in the channel regions} - H10D 48/383: {Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects} - H10D 48/3835: {Semiconductor qubit devices comprising a plurality of quantum mechanically interacting semiconductor quantum dots, e.g. Loss-DiVincenzo spin qubits} - H10D 62/814: {Quantum box structures} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge - H10D 64/27: Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates - H10D 64/518: {characterised by their lengths or sectional shapes} - H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT] - H10D 48/40: Devices controlled by magnetic fields - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material disposed above the quantum well stack, wherein the insulating material includes a trench; and a gate metal disposed on the insulating material and extending into the trench. ## Claims ### Claim 1 A device, comprising: a quantum well stack of a quantum dot device; an insulating material above the quantum well stack, wherein the insulating material includes a first trench and a second trench; a first gate metal on the insulating material and extending into the first trench; and a second gate metal on the insulating material and extending into the second trench. ### Claim 2 (depends on 1) The device of claim 1, wherein the first and second trenches are parallel. ### Claim 3 (depends on 1) The device of claim 1, wherein the first and second trenches are spaced apart by a distance between 50 and 250 nanometers. ### Claim 4 (depends on 1) The device of claim 1, wherein the first trench has a tapered profile that is narrowest proximate to the quantum well stack. ### Claim 5 (depends on 1) The device of claim 1, wherein the first trench extends down to the quantum well stack. ### Claim 6 (depends on 1) The device of claim 1, further comprising: a semiconductor substrate, wherein the quantum well stack is on the semiconductor substrate. ### Claim 7 (depends on 1) The device of claim 1, wherein a gate dielectric is at a bottom of the trench. ### Claim 8 (depends on 1) The device of claim 1, further comprising: a magnet line. ### Claim 9 (depends on 1) The device of claim 1, wherein the quantum well stack includes a silicon/silicon germanium material stack. ### Claim 10 (depends on 1) The device of claim 1, further comprising: a third gate metal on the insulating material and extending into the first trench, wherein the third gate metal is electrically insulated from the first gate metal. ### Claim 11 (depends on 10) The device of claim 10, further comprising: spacer material between the first gate metal and the third gate metal. ### Claim 12 (depends on 10) The device of claim 10, further comprising: spacer material between the third gate metal in the first trench and sidewalls of the first trench. ### Claim 13 A method of operating a quantum dot device, comprising: providing electrical signals to one or more gates at least partially in a first trench in an insulating material to cause a first quantum dot to form in a quantum well stack below the first trench; providing electrical signals to one or more gates at least partially in a second trench in the insulating material to cause a second quantum dot to form in the quantum well stack; and sensing a quantum state of the first quantum dot with the second quantum dot. ### Claim 14 (depends on 13) The method of claim 13, further comprising: providing electrical signals to the one or more gates at least partially in the first trench to cause a third quantum dot to form in the quantum well stack; and prior to sensing the quantum state of the first quantum dot with the second quantum dot, allowing the first and third quantum dots to interact. ### Claim 15 A method of manufacturing a quantum dot device, comprising: providing a quantum well stack on a substrate; providing an insulating material above the quantum well stack, wherein the insulating material includes a trench; and forming gates on the insulating material, wherein the gates extend into the trench. ### Claim 16 (depends on 15) The method of claim 15, wherein providing the insulating material on the quantum well stack includes: depositing the insulating material above the quantum well stack; and removing at least some of the insulating material to form the trench. ### Claim 17 A quantum computing device, comprising: a quantum processing device, wherein the quantum processing device includes an insulating material having first and second trenches that extend toward a quantum well stack, gate metal of an active quantum dot formation gate on the insulating material and extending into the first trench, and gate metal of a read quantum dot formation gate on the insulating material and extending into the second trench; a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the active quantum dot formation gates and the read quantum dot formation gate; and a memory device to store data generated by quantum dots read by the read quantum dot formation gates during operation of the quantum processing device. ### Claim 18 (depends on 17) The quantum computing device of claim 17, wherein the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device. ### Claim 19 (depends on 17) The quantum computing device of claim 17, wherein a quantum dot read by the read quantum dot formation gates is formed in a same quantum well layer in the quantum well stack as a quantum dot induced by the active quantum dot formation gate.