# US 10,770,544 B2 · Semiconductor devices

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- Number: US 10,770,544 B2
- Document ID: US10770544B2
- Status: Granted
- Kind: B2
- Application number: 16/725,076
- Filed: 2019-12-23
- Published: 2020-05-07
- Granted: 2020-09-08
- Earliest claimed: 2017-12-04
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jee Yong Kim; Jung Hwan Lee
- Web page: https://patentgrep.com/patent/US10770544B2

## CPC

- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device includes a substrate including a recess, the recess being positioned below an isolation region and having a side portion including a plurality of stepped portions, a plurality of gate electrodes spaced apart from each other on the substrate, and stacked in a direction perpendicular to an upper surface of the substrate, a channel structure passing between a first set of the plurality of gate electrodes, and the isolation region passing between a second set of the plurality of gate electrodes, the isolation region extending from the upper surface of the substrate and having an inclined lateral surface.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate including a recess, the substrate defining the recess to include a first region, a second region and a third region having different widths;
a stack structure including a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the substrate;
a common source pattern passing through the stack structure to contact the substrate at the first region of the recess; and
an insulating spacer between the stack structure and the common source pattern, the insulating spacer including silicon nitride.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the common source pattern extends in a direction parallel to an upper surface of the substrate, and the insulating spacer including a combination of two or more of silicon compound containing oxygen, silicon compound containing nitrogen.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a first space between a lateral surface of a lowermost gate electrode of the plurality of gate electrodes and the common source pattern is different from a second space between a lateral surface of the substrate at the second region of the recess and the common source pattern, and a lower portion of the insulating spacer includes a bent portion formed according to a shape of the recess, and contacts the substrate at the second region and the third region of the recess.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
a peripheral circuit region below the substrate and on a base substrate, the peripheral circuit region including a plurality of transistors and a plurality of wirings, and the peripheral circuit region overlapping the stack structure in a direction perpendicular to an upper surface of the substrate.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second region is above the first region, the third region is above the second region, and
a first width of the first region is narrower than a second width of the second region, and the second width of the second region is narrower than a third width of the third region, and
a lateral surface of the third region is coplanar with a lateral surface of a lowermost mold insulating layer of the plurality of mold insulating layers, the lowermost mold insulating layer contacting an upper surface of the substrate.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first upper insulating layer on the stack structure; and
a second upper insulating layer on the first upper insulating layer and the common source pattern.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further comprising:
a channel structure passing through the stack structure; and
a contact plug passing through the second upper insulating layer, and electrically connecting to the channel structure.

### Claim 8

A semiconductor device comprising:
a substrate including a recess, the substrate defining the recess to include a first region, a second region and a third region having different widths;
a stack structure including a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the substrate;
a common source pattern passing through the stack structure to contact the substrate at the first region of the recess; and
an insulating spacer between the stack structure and the common source pattern, the insulating spacer including silicon compound containing nitrogen.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the common source pattern extends in a direction parallel to an upper surface of the substrate, and the insulating spacer including a combination of two or more of silicon compound containing oxygen, silicon compound containing nitrogen.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the insulating spacer includes a plurality of stepped portions below a lowermost gate electrode of the plurality of gate electrodes.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein a first space between a lateral surface of a lowermost gate electrode of the plurality of gate electrodes and the common source pattern is different from a second space between a lateral surface of the substrate at the second region of the recess and the common source pattern, and
a lower portion of the insulating spacer includes a bent portion formed according to a shape of the recess, and contacts the substrate at the second region and the third region of the recess.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, further comprising:
a peripheral circuit region below the substrate and on a base substrate, the peripheral circuit region including a plurality of transistors and a plurality of wirings, and the peripheral circuit region overlapping the stack structure in a direction perpendicular to an upper surface of the substrate.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein the second region is above the first region, the third region is above the second region, and
a first width of the first region is narrower than a second width of the second region, and the second width of the second region is narrower than a third width of the third region, and
a lateral surface of the third region is coplanar with a lateral surface of a lowermost mold insulating layer of the plurality of mold insulating layers, the lowermost mold insulating layer contacting an upper surface of the substrate.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, further comprising:
a first upper insulating layer on the stack structure, and
wherein the common source pattern cuts the first upper insulating layer and the stack structure in a direction parallel to an upper surface of the substrate, and vertically penetrates the first upper insulating layer.

### Claim 15 (depends on 8)

The semiconductor device of claim 8, further comprising;
a first upper insulating layer on the stack structure; and
a second upper insulating layer on the first upper insulating layer and the common source pattern.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, further comprising;
a channel structure passing through the stack structure; and
a contact plug passing through the second upper insulating layer, and electrically connecting to the channel structure.

### Claim 17

A semiconductor device comprising:
a substrate including a recess, the substrate defining the recess to include a first region, a second region and a third region having different widths;
a stack structure including a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the substrate;
a peripheral circuit region below the substrate and on a base substrate, the peripheral circuit region including a plurality of transistors and a plurality of wirings, the peripheral circuit region overlapping the stack structure in a direction perpendicular to an upper surface of the substrate;
a common source pattern passing through the stack structure to contact the substrate at the first region of the recess, the common source pattern extending in a direction parallel to an upper surface of the substrate; and
an insulating spacer between the stack structure and the common source pattern, the insulating spacer including silicon compound containing nitrogen.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the insulating spacer including a combination of two or more of silicon compound containing oxygen, silicon compound containing nitrogen.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the insulating spacer includes a plurality of stepped portions below a lowermost gate electrode of the plurality of gate electrodes.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, wherein a first space between a lateral surface of a lowermost gate electrode of the plurality of gate electrodes and the common source pattern is different from a second space between a lateral surface of the substrate at the second region of the recess and the common source pattern, and
a lower portion of the insulating spacer includes a bent portion formed according to a shape of the recess, and contacts the substrate at the second region and the third region of the recess.

### Claim 21 (depends on 17)

The semiconductor device of claim 17, wherein the second region is above the first region, the third region is above the second region, and
a first width of the first region is narrower than a second width of the second region, and the second width of the second region is narrower than a third width of the third region, and
a lateral surface of the third region is coplanar with a lateral surface of a lowermost mold insulating layer of the plurality of mold insulating layers, the lowermost mold insulating layer contacting an upper surface of the substrate.

### Claim 22 (depends on 17)

The semiconductor device of claim 17, further comprising;
a first upper insulating layer on the stack structure; and
a second upper insulating layer on the first upper insulating layer and the common source pattern.

### Claim 23 (depends on 22)

The semiconductor device of claim 22, further comprising;
a channel structure passing through the stack structure; and
a contact plug passing through the second upper insulating layer, and electrically connecting to the channel structure.

### Claim 24

A semiconductor device comprising:
a substrate including a recess, the substrate defining the recess to include a first region, a second region and a third region having different widths;
a stack structure including a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the substrate;
a peripheral circuit region below the substrate and on a base substrate, the peripheral circuit region including a plurality of transistors and a plurality of wirings, the peripheral circuit region overlapping the stack structure in a direction perpendicular to an upper surface of the substrate;
a common source pattern passing through the stack structure to contact the substrate at the first region of the recess;
an insulating spacer between the stack structure and the common source pattern, the insulating spacer including silicon compound containing nitrogen;
an upper insulating layer on the stack structure;
a channel structure passing through the stack structure; and
a contact plug passing through the upper insulating layer, and electrically connecting to the channel structure.

### Claim 25 (depends on 24)

The semiconductor device of claim 24, wherein the insulating spacer including a combination of two or more of silicon compound containing oxygen, silicon compound containing nitrogen.

### Claim 26 (depends on 24)

The semiconductor device of claim 24, wherein the substrate defining a side portion of the recess to include a plurality of stepped portions.

### Claim 27 (depends on 24)

The semiconductor device of claim 24, wherein the common source pattern extends in a direction parallel to an upper surface of the substrate.

### Claim 28 (depends on 24)

The semiconductor device of claim 24, wherein the common source pattern cuts the upper insulating layer and the stack structure in a direction parallel to an upper surface of the substrate, and vertically penetrates the upper insulating layer.

### Claim 29 (depends on 24)

The semiconductor device of claim 24, wherein a first space between a lateral surface of a lowermost gate electrode of the plurality of gate electrodes and the common source pattern is different from a second space between a lateral surface of the substrate at the second region of the recess and the common source pattern, and
a lower portion of the insulating spacer includes a bent portion formed according to a shape of the recess, and contacts the substrate at the second region and the third region of the recess.

### Claim 30 (depends on 24)

The semiconductor device of claim 24, wherein the second region is above the first region, the third region is above the second region, and
a first width of the first region is narrower than a second width of the second region, and the second width of the second region is narrower than a third width of the third region, and
a lateral surface of the third region is coplanar with a lateral surface of a lowermost mold insulating layer of the plurality of mold insulating layers, the lowermost mold insulating layer contacting an upper surface of the substrate.