# US 10,770,543 B2 · Semiconductor chip integrating high and low voltage devices

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- Number: US 10,770,543 B2
- Document ID: US10770543B2
- Status: Granted
- Kind: B2
- Application number: 16/191,070
- Filed: 2018-11-14
- Published: 2019-03-21
- Granted: 2020-09-08
- Earliest claimed: 2011-09-20
- Assignees: Alpha and Omega Semiconductor Incorporated
- Applicants: Alpha and Omega Semiconductor Incorporated
- Inventors: Hideaki Tsuchiko
- Web page: https://patentgrep.com/patent/US10770543B2

## CPC

- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 8/411: {PN diodes having planar bodies}
- H10D 10/051: {of vertical BJTs (of heterojunction BJTs H10D10/021; of Schottky BJTs H10D10/031; of thin film BJTs H10D10/041)}
- H10D 10/40: Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)}
- H10D 10/60: Lateral BJTs
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/17: Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D 62/364: {of IGFETs}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 84/0112: {Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs}
- H10D 84/0119: {the components including complementary BJTs}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0156: {Manufacturing their doped wells}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10D 84/403: {Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors}
- H10D 84/63: Combinations of vertical and lateral BJTs
- H10D 84/641: {Combinations of only vertical BJTs (vertical complementary BJTs H10D84/673)}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10W 10/30: Isolation regions comprising PN junctions
- H10D 64/516: {the thicknesses being non-uniform}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention is directed to a semiconductor chip comprising a high voltage device and a low voltage device disposed thereon. The chip may be formed in several different configurations. For example, the semiconductor chip may include a NPN bipolar transistor, PNP bipolar transistor, a diode, an N channel DMOS transistor and the like. the first doped well being configured as a base of the DMOS transistor, a P channel DMOS transistor and the like. These and other embodiments are described in further detail below.

## Claims

### Claim 1

A semiconductor chip comprising a high voltage device and a low voltage device disposed thereon, said semiconductor chip further comprising:
a substrate layer of a first conductivity type;
a first epitaxial layer of the first conductivity type on a top surface of the substrate layer;
a second epitaxial layer of a second conductivity opposite to the first conductivity type on a top surface of the first epitaxial layer;
a deep buried implant region of the second conductivity type in an area for the high voltage device;
a buried implant region of the second conductivity type in an area for the low voltage device; and
a first doped well of the first conductivity type extending from a top surface of the second epitaxial layer above the deep buried implant region; and a second doped well of the first conductivity type from a top surface of the second epitaxial layer above the buried implant region, wherein the second doped well of the first conductivity type has a greater doping concentration than the first epitaxial layer and substrate.

### Claim 2 (depends on 1)

The semiconductor chip as recited in claim 1 wherein the dopant concentration of the first epitaxial layer being substantially the same as the substrate.

### Claim 3

A semiconductor chip comprising a high voltage device and a low voltage device disposed thereon, said semiconductor chip further comprising:
a substrate layer of a first conductivity type;
a first epitaxial layer of the first conductivity type on a top surface of the substrate layer;
a second epitaxial layer of a second conductivity opposite to the first conductivity type on a top surface of the first epitaxial layer;
a deep buried implant region of the second conductivity type in an area for the high voltage device, wherein the deep buried implant region of the second conductivity type further comprises a deep buried highly doped region of the second conductivity type and a deep buried lightly doped region of the second conductivity type surrounding the deep buried highly doped region;
a buried implant region of the second conductivity type in an area for the low voltage device; and
a first doped well of the first conductivity type extending from a top surface of the second epitaxial layer above the deep buried implant region; and a second doped well of the first conductivity type from a top surface of the second epitaxial layer above the buried implant region.

### Claim 4 (depends on 3)

The semiconductor chip as recited in claim 3 wherein the deep buried lightly doped region extending from a depth of the substrate to a top surface of the first epitaxial layer and having a doping concentration substantially the same as the second epitaxial layer.

### Claim 5 (depends on 4)

The semiconductor chip as recited in claim 4 further comprising isolation regions surrounding active areas of the high voltage device and low voltage device.

### Claim 6

A semiconductor chip comprising a high voltage device and a low voltage device disposed thereon, said semiconductor chip further comprising:
a substrate layer of a first conductivity type;
a first epitaxial layer of the first conductivity type on a top surface of the substrate layer, with the dopant concentration of the first epitaxial layer being substantially the same as the substrate;
a second epitaxial layer of a second conductivity opposite to the first conductivity type on a top surface of the first epitaxial layer;
a deep buried implant region of the second conductivity type in an area for the high voltage device, said deep buried region includes a highly doped region of the second conductivity type and a deep buried lightly doped region of the second conductivity type surrounding the deep buried highly doped region;
a buried implant region of the second conductivity type in an area for the low voltage device;
a first doped well of the first conductivity type extending from a top surface of the second epitaxial layer above the deep buried implant region; and a second doped well of the first conductivity type from a top surface of the second epitaxial layer above the buried implant region; and
isolation regions surrounding active areas of the high voltage device and said low voltage device.

### Claim 7 (depends on 6)

The semiconductor chip as recited in claim 6 wherein the deep buried lightly doped region extending from a depth of the substrate to a top surface of the first epitaxial layer and having a doping concentration substantially the same as the second epitaxial layer.