# US 10,770,541 B2 · Semiconductor device including super junction structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,541 B2 - Document ID: US10770541B2 - Status: Granted - Kind: B2 - Application number: 16/394,653 - Filed: 2019-04-25 - Published: 2019-08-15 - Granted: 2020-09-08 - Earliest claimed: 2016-08-25 - Assignees: Infineon Technologies Austria AG - Applicants: Infineon Technologies Austria AG - Inventors: Franz Hirler; Hans Weber - Web page: https://patentgrep.com/patent/US10770541B2 ## CPC - H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures} - H10D 30/0281: {of lateral DMOS [LDMOS] FETs} - H10D 30/0291: {of vertical DMOS [VDMOS] FETs} - H10D 30/0295: {using recessing of the source electrodes} - H10D 30/65: Lateral DMOS [LDMOS] FETs - H10D 30/66: Vertical DMOS [VDMOS] FETs - H10D 30/665: {having edge termination structures} - H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)} - H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)} - H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers} - H10D 62/60: Impurity distributions or concentrations - H10D 64/111: {Field plates} - H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device of an embodiment includes transistor cells in a transistor cell area of a semiconductor body. A super junction structure in the semiconductor body includes a plurality of drift sub-regions and compensation sub-regions of opposite first and second conductivity types, respectively, and alternately arranged along a lateral direction. A termination area outside the transistor cell area between an edge of the semiconductor body and the transistor cell area includes first and third termination sub-regions of the first conductivity type, respectively. A second termination sub-region of the second conductivity type is sandwiched between the first and the third termination sub-regions along a vertical direction perpendicular to a first surface of the semiconductor body. ## Claims ### Claim 1 A semiconductor device, comprising: transistor cells in a transistor cell area of a semiconductor body; a super junction structure in the semiconductor body, the super junction structure comprising a plurality of drift sub-regions and compensation sub-regions of opposite first and second conductivity types, respectively, and alternately arranged along a lateral direction, wherein each of the drift sub-regions include first dopants of the first conductivity type partially compensated by second dopants of the second conductivity type; and a termination area outside the transistor cell area between an edge of the semiconductor body and the transistor cell area, the termination area comprising first and third termination sub-regions of the first conductivity type, respectively, and a second termination sub-region of the second conductivity type sandwiched between the first and the third termination sub-regions along a vertical direction perpendicular to a first surface of the semiconductor body, wherein the first and the third termination sub-regions merge and fully surround the second termination sub-region. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein an extension of the second termination sub-region along the vertical direction ranges between 20% and 80% of a vertical distance between a bottom side of the compensation sub-regions and the first surface. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the second termination sub-region is electrically floating. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the second termination sub-region is of the second conductivity type and includes dopants of the second conductivity type partially compensated by dopants of the first conductivity type. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein each of the first and the third termination sub-regions is of the first conductivity type and includes dopants of the first conductivity type partially compensated by dopants of the second conductivity type. ### Claim 6 (depends on 4) The semiconductor device of claim 4, wherein a pair of dopants of the first and the second conductivity types corresponds to one of As and B, As and Al, Sb and B, Sb and Al, P and Al. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein an extension of the second termination sub-region ranges between 3×p and 15×p, p being a pitch of the compensation sub-regions. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the second termination sub-region surrounds the transistor cell area. ### Claim 9 (depends on 1) The semiconductor device of claim 1, further comprising a field stop region of the first conductivity type between the edge of the semiconductor body and the second termination sub-region. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein a vertical extension of the field stop region ranges between 50% and 110% of a vertical extension of the compensation sub-regions. ### Claim 11 (depends on 1) The semiconductor device of claim 1, further comprising a fourth termination sub-region of the second conductivity type sandwiched between the first termination sub-region and the first surface. ### Claim 12 (depends on 1) The semiconductor device of claim 1, further comprising a fifth termination sub-region of the second conductivity type sandwiched between the third termination sub-region and a semiconductor substrate of the first conductivity type. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein a vertical distance between the fifth termination sub-region and the first surface ranges between 80% and 100% of a vertical distance between a bottom side of the compensation sub-regions and the first surface. ### Claim 14 (depends on 1) The semiconductor device of claim 1, wherein the semiconductor device is a vertical power transistor comprising a first load terminal contact at the first surface of the semiconductor body and a second load terminal contact at a second surface of the semiconductor body opposite to the first surface. ### Claim 15 A semiconductor device, comprising: transistor cells in a transistor cell area of a semiconductor body; a super junction structure in the semiconductor body, the super junction structure comprising a plurality of drift sub-regions and compensation sub-regions of opposite first and second conductivity types, respectively, and alternately arranged along a lateral direction, wherein each of the drift sub-regions include first dopants of the first conductivity type partially compensated by second dopants of the second conductivity type; and a termination area outside the transistor cell area between an edge of the semiconductor body and the transistor cell area, the termination area comprising first and third termination sub-regions of the first conductivity type, respectively, and a second termination sub-region of the second conductivity type sandwiched between the first and the third termination sub-regions along a vertical direction perpendicular to a first surface of the semiconductor body, wherein the semiconductor device further comprises a fifth termination sub-region of the second conductivity type sandwiched between the third termination sub-region and a semiconductor substrate of the first conductivity type. ### Claim 16 A semiconductor device, comprising: transistor cells in a transistor cell area of a semiconductor body; a super junction structure in the semiconductor body, the super junction structure comprising a plurality of drift sub-regions and compensation sub-regions of opposite first and second conductivity types, respectively, and alternately arranged along a lateral direction, wherein each of the drift sub-regions include first dopants of the first conductivity type partially compensated by second dopants of the second conductivity type; and a termination area outside the transistor cell area between an edge of the semiconductor body and the transistor cell area, the termination area comprising first and third termination sub-regions of the first conductivity type, respectively, and a second termination sub-region of the second conductivity type sandwiched between the first and the third termination sub-regions along a vertical direction perpendicular to a first surface of the semiconductor body, wherein the second termination sub-region is electrically floating.