# US 10,770,490 B2 · Semiconductor device and electronic apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,490 B2 - Document ID: US10770490B2 - Status: Granted - Kind: B2 - Application number: 16/438,116 - Filed: 2019-06-11 - Published: 2019-09-26 - Granted: 2020-09-08 - Earliest claimed: 2015-03-03 - Assignees: Sony Corporation - Applicants: Sony Corporation - Inventors: Yukihiro Ando - Web page: https://patentgrep.com/patent/US10770490B2 ## CPC - H10W 78/00: Detachable holders for supporting packaged chips in operation - H04N 25/70: SSIS architectures; Circuits associated therewith - H10F 39/026: {Wafer-level processing} - H10F 39/12: Image sensors - H10F 39/80: {Constructional details of image sensors} - H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes} - H10F 39/809: {of hybrid image sensors} - H10F 39/811: {Interconnections} - H10F 99/00: Subject matter not provided for in other groups of this subclass - H10P 14/40: of conductive or resistive materials - H10W 20/01: {Manufacture or treatment} - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 70/20: Conductive package substrates serving as an interconnection, e.g. metal plates (leadframes H10W70/40) - H10W 72/00: Interconnections or connectors in packages - H10W 72/90: Bond pads, in general - H10W 72/019: {of bond pads} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 80/701: {characterised by the pads after the direct bonding} - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure relates to a semiconductor device and an electronic apparatus which is capable of reducing variations and deterioration of transistor characteristics. A first connection pad connected with a first wiring and a first floating metal greater than the first connection pad are formed at a bonding surface of a first substrate, whereas a second connection pad connected with a second wiring and a second floating metal greater than the second connection pad are formed at a bonding surface of a second substrate. The first floating metal and the second floating metal formed at the first substrate and the second substrate are bonded to each other. The present disclosure is applicable to a CMOS solid-state imaging device used for an imaging apparatus such as a camera, for example. ## Claims ### Claim 1 A semiconductor device comprising: a first substrate; and a second substrate bonded to the first substrate, wherein the first substrate includes: a first floating metal formed at a bonding surface between the first substrate and the second substrate; a first pad formed at the bonding surface and spaced apart from the first floating metal by part of the first substrate; and a first wiring connected to the first pad, wherein the second substrate includes: a second floating metal formed at the bonding surface; a second pad formed at the bonding surface and spaced apart from the second floating metal by part of the second substrate; and a second wiring connected to the second pad, wherein the first pad is bonded to the second floating metal, the first floating metal is bonded to the second floating metal, and the second pad is bonded to the first floating metal, wherein, in a plan view, the first floating metal overlaps the second floating metal, wherein, in the plan view, the first pad overlaps the second floating metal, and wherein, in the plan view, the second pad overlaps the first floating metal. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein, in the plan view, the second floating metal completely overlaps the first pad. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein, in the plan view, the first floating metal completely overlaps the second pad. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the first floating metal is formed in such a manner as to have a vacant space in a first central area corresponding to a central portion of the first floating metal and to surround the first pad formed in the first central area, and the second floating metal is formed in such a manner as to have a vacant space in a second central area corresponding to a central portion of the second floating metal and to surround the second pad formed in the second central area. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the first floating metal and the first pad are formed in circular shapes at the bonding surface, and the second floating metal and the second pad are formed in circular shapes at the bonding surface. ### Claim 6 (depends on 4) The semiconductor device according to claim 4, wherein the first floating metal and the first pad are formed in rectangular shapes at the bonding surface of the first substrate, and the second floating metal and the second pad are formed in rectangular shapes at the bonding surface of the second substrate. ### Claim 7 (depends on 4) The semiconductor device according to claim 4, wherein the first floating metal is configured at the bonding surface in such a shape that, in either one of a transverse direction or a longitudinal direction of a rectangle with a vacant space in the first central area, a plurality of slits oriented in another direction are arranged, and the second floating metal is configured at the bonding surface in such a shape that, in the other of the transverse and longitudinal direction of a rectangle with a vacant space in the second central area, a plurality of slits oriented in the one direction are arranged. ### Claim 8 (depends on 4) The semiconductor device according to claim 4, wherein the first floating metal is configured at the bonding surface in such a shape that a plurality of blocks are each overlapping with at least one adjacent block at corners thereof while having a vacant space in the first central area, and the second floating metal is configured at the bonding surface in such a shape that a plurality of blocks are each overlapping with at least one adjacent block at corners thereof while having a vacant space in the second central area. ### Claim 9 (depends on 2) The semiconductor device according to claim 2, wherein the semiconductor device is a solid-state imaging device. ### Claim 10 An electronic apparatus comprising: a solid-state imaging device which includes: a first substrate; and a second substrate bonded to the first substrate, wherein the first substrate includes: a first floating metal formed at a bonding surface between the first substrate and the second substrate, wherein the first substrate includes: a first pad formed at the bonding surface and spaced apart from the first floating metal by part of the first substrate; and a first wiring connected to the first pad, wherein the second substrate includes: a second floating metal formed at the bonding surface; a second pad formed at the bonding surface and spaced apart from the second floating metal by part of the second substrate; and a second wiring connected to the second pad, wherein the first pad is bonded to the second floating metal, the first floating metal is bonded to the second floating metal, and the second pad is bonded to the first floating metal, wherein, in a plan view, the first floating metal overlaps the second floating metal, wherein, in the plan view, the first pad overlaps the second floating metal, and wherein, in the plan view, the second pad overlaps the first floating metal; a signal processing circuit which processes an output signal outputted from the solid-state imaging device; and an optical system which directs light to the solid-state imaging device.