# US 10,770,488 B2 · Active switch array substrate and method for manufacturing the same

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- Number: US 10,770,488 B2
- Document ID: US10770488B2
- Status: Granted
- Kind: B2
- Application number: 16/317,045
- Filed: 2017-12-04
- Published: 2019-10-03
- Granted: 2020-09-08
- Earliest claimed: 2016-12-08
- Assignees: Hkc Corporation Limited; Chongqing Hkc Optoelectronics Technology Co., Ltd.
- Applicants: HKC Corporation Limited; Chongqing HKC Optoelectronics Technology Co., Ltd.
- Inventors: En-tsung Cho
- Web page: https://patentgrep.com/patent/US10770488B2

## CPC

- H10D 86/0251: {characterised by increasing the uniformity of device parameters}
- G02F 1/13439: {characterised by their electrical, optical, physical properties; materials therefor; method of making}
- G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6732: {Bottom-gate only TFTs}
- H10D 30/6737: {characterised by the electrode materials}
- H10D 30/6743: {Silicon}
- H10D 30/6746: {Amorphous silicon}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

The present disclosure provides a method for manufacturing an active switch array substrate, and the active switch array substrate, the method includes: providing a substrate; coating a first metal layer on the substrate; forming a gate electrode by treating the first metal layer; depositing an amorphous silicon layer on the substrate and the gate electrode; coating a second metal layer on the amorphous silicon layer; forming a patterned second metal layer; coating a passivation layer on the patterned second metal layer; forming a through hole in the passivation layer; coating a light permeability conductive layer on the passivation layer; and carrying out a fourth photolithography process to the light permeability conductive layer, the passivation layer, and the patterned second metal layer, to form a channel, a source electrode, and a drain electrode on the light permeability conductive layer, the passivation layer, and the patterned second metal layer.

## Claims

### Claim 1

A method for manufacturing an active switch array substrate, comprising the following steps:
providing a substrate;
coating a first metal layer on the substrate;
forming a gate electrode by treating the first metal layer through a first photolithography process;
depositing an amorphous silicon layer on the substrate and the gate electrode;
coating a second metal layer on the amorphous silicon layer;
forming a patterned second metal layer by treating the second metal layer through a second photolithography process;
coating a passivation layer on the patterned second metal layer;
forming a through hole in the passivation layer by treating the passivation layer through a third photolithography process;
coating a light permeability conductive layer on the passivation layer, the light permeability conductive layer passing through the through hole to contact with the patterned second metal layer; and
carrying out a fourth photolithography process to the light permeability conductive layer, the passivation layer, and the patterned second metal layer, to form a channel, a source electrode, and a drain electrode on the light permeability conductive layer, the passivation layer, and the patterned second metal layer, the source electrode and the drain electrode being located at two sides of the channel respectively, wherein the channel is separated from the through hole.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the step of forming the channel comprises the following steps:
coating a photo-resist film on the light permeability conductive layer;
providing a binary mask which comprises two portions having different transmittance;
shielding the photo-resist film using the binary mask;
after ultraviolet light passing through the binary mask, the ultraviolet light irradiating a first portion of the photo-resist film; removing the first portion of the photo-resist film, remaining a second portion of the photo-resist film;
removing the light permeability conductive layer, the passivation layer, and the patterned second metal layer exposed from the second portion of the photo-resist film, forming the channel.

### Claim 3 (depends on 1)

The method according to claim 1, wherein a width of the channel is 2 μm to 5 μm.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the step of coating the first metal layer on the substrate comprises: coating a first metal composite layer on the substrate, the first metal composite layer being a molybdenum-aluminum composite layer, a molybdenum-aluminum alloy composite layer, a titanium-aluminum composite layer, or a copper-molybdenum composite layer.

### Claim 5 (depends on 4)

The method according to claim 4, wherein the step of coating the second metal layer on the amorphous silicon layer comprises: coating a second metal composite layer on the amorphous silicon layer, the second metal composite layer being a molybdenum-aluminum-molybdenum composite layer, a titanium-aluminum-titanium composite layer, or a copper-molybdenum composite layer.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the light permeability conductive layer is a semi-transparent or transparent conductive metal layer.

### Claim 7

An active switch array substrate, comprising:
a substrate;
a gate electrode, defined on the substrate;
an amorphous silicon layer, defined on a surface of the substrate and a surface the gate electrode;
a patterned second metal layer, defined on a surface of the amorphous silicon layer;
a passivation layer, defined on a surface of the patterned second metal layer and the surface of the amorphous silicon layer, the passivation layer defining a through hole; and
a pixel electrode, formed in the passivation layer, the pixel electrode passing through the through hole to contact with the patterned second metal layer, the patterned second metal layer, the passivation layer, and the pixel electrode cooperatively forming a channel through a photolithography process, the channel dividing the patterned second metal layer to form a source electrode and a drain electrode, the channel being separated from the through hole.

### Claim 8 (depends on 7)

The active switch array substrate according to claim 7, wherein a width of the channel is 2 μm to 5 μm.

### Claim 9 (depends on 7)

The active switch array substrate according to claim 7, wherein the gate electrode is a first metal composite layer, the first metal composite layer is a molybdenum-aluminum composite layer, a molybdenum-aluminum alloy composite layer, a titanium-aluminum composite layer, or a copper-molybdenum composite layer.

### Claim 10 (depends on 7)

The active switch array substrate according to claim 7, wherein the second metal layer is a second metal composite layer, the second metal composite layer is a molybdenum-aluminum-molybdenum composite layer, a titanium-aluminum-titanium composite layer, or a copper-molybdenum composite layer.

### Claim 11 (depends on 7)

The active switch array substrate according to claim 7, wherein the pixel electrode is indium tin oxide.

### Claim 12 (depends on 7)

The active switch array substrate according to claim 7, wherein the passivation layer is made of SiNx, a thickness of the passivation layer is 100 μm to 250 μm, x equates to one or three-quarters.

### Claim 13 (depends on 7)

The active switch array substrate according to claim 7, wherein the amorphous silicon layer comprises a SiNx layer, an α-Si layer, and a N+α-Si layer which are formed on the substrate and the gate electrode in sequence.

### Claim 14 (depends on 7)

The active switch array substrate according to claim 7, wherein a data line is formed on the substrate and is interlaced with the gate electrode.

### Claim 15

An active switch array substrate, wherein, the active switch array substrate comprises:
a substrate;
a gate electrode, defined on the substrate, the gate electrode is a first metal composite layer, the first metal composite layer is a molybdenum-aluminum composite layer, a molybdenum-aluminum alloy composite layer, a titanium-aluminum composite layer, or a copper-molybdenum composite layer;
an amorphous silicon layer, defined on a surface of the substrate and a surface the gate electrode;
a patterned second metal layer, defined on a surface of the amorphous silicon layer, the second metal layer is a second metal composite layer, the second metal composite layer is a molybdenum-aluminum-molybdenum composite layer, a titanium-aluminum-titanium composite layer, or a copper-molybdenum composite layer;
a passivation layer, defined on a surface of the patterned second metal layer and the surface of the amorphous silicon layer, the passivation layer defines a through hole; and
a pixel electrode, formed in the passivation layer, the pixel electrode passes through the through hole to contact with the second metal layer, the patterned second metal layer, the passivation layer, and the pixel electrode cooperatively form a channel through a photolithography process, the channel divides the patterned second metal layer to form a source electrode and a drain electrode, a width of the channel is 2 μm to 5 μm, the channel is separated from the through hole.