# US 10,770,484 B2 · Thin film transistor, a method of manufacturing the same, and a display apparatus including the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,770,484 B2
- Document ID: US10770484B2
- Status: Granted
- Kind: B2
- Application number: 16/298,270
- Filed: 2019-03-11
- Published: 2019-07-04
- Granted: 2020-09-08
- Earliest claimed: 2016-05-20
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Sun Park; Chungi You; Hyuksoon Kwon
- Web page: https://patentgrep.com/patent/US10770484B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/427: {having different thicknesses of the semiconductor bodies in different TFTs}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10K 59/122: Pixel-defining structures or layers, e.g. banks
- H10K 59/123: Connection of the pixel electrodes to the thin film transistors [TFT]
- H10K 59/38: comprising colour filters or colour changing media [CCM]
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A thin film transistor including a substrate; a semiconductor layer disposed over the substrate; a gate insulting film disposed over the semiconductor layer; and a gate electrode. The semiconductor layer includes a channel region, a source region, and a drain region. The gate insulating film includes a first region and a second region. The second region borders the first region. The gate electrode is disposed over the first region. A step shape is formed where the second region meets the first region.

## Claims

### Claim 1

A method of manufacturing a thin film transistor, the method comprising:
forming a semiconductor layer over a substrate;
sequentially forming a gate insulating material layer and a gate electrode material layer on the substrate to cover the semiconductor layer;
forming a first photoresist pattern on the gate electrode material layer;
forming a gate electrode by etching the gate electrode material layer using the first photoresist pattern as a mask;
forming a second photoresist pattern covering both sidewalls and an upper surface of the gate electrode; and
forming a gate insulating film by etching the gate insulating material layer using the second photoresist pattern as a mask, the gate insulating film including a first region and a second region having portions disposed at opposite sides of the first region, and a thickness of the first region is different than a thickness of the portions of the second region,
wherein a portion of the first region and the portions of the second region do not overlap the gate electrode in a thickness direction of the substrate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second photoresist pattern is formed by reflowing the first photoresist pattern.

### Claim 3 (depends on 1)

The method of claim 1, further comprising performing a conducting process to increase a carrier concentration of a portion of the semiconductor layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein the etching of the gate insulating material layer comprises a dry etching process, and the conducting process uses a gas used in the dry etching process.

### Claim 5 (depends on 1)

The method of claim 1, wherein a step shape is included in the gate insulating film at a boundary between the first region and the second region.

### Claim 6 (depends on 5)

The method of claim 5, wherein the gate electrode is disposed on the first region, and a width of an upper surface of the first region in a direction parallel to a top surface of the substrate is greater than a width of a lower surface of the gate electrode in the direction parallel to the top surface of the substrate.

### Claim 7 (depends on 5)

The method of claim 5, wherein a thickness of the second region is gradually reduced in a direction away from the first region.

### Claim 8 (depends on 1)

The method of claim 1, wherein the semiconductor layer comprises an oxide semiconductor.

### Claim 9 (depends on 1)

The method of claim 1, wherein a buffer layer is formed on the substrate and the buffer layer is positioned between the semiconductor layer and the substrate.