# US 10,770,481 B2 · Semiconductor device and method for manufacturing the same

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- Number: US 10,770,481 B2
- Document ID: US10770481B2
- Status: Granted
- Kind: B2
- Application number: 16/123,634
- Filed: 2018-09-06
- Published: 2019-03-14
- Granted: 2020-09-08
- Earliest claimed: 2017-09-11
- Assignees: NuFlare Technology, Inc.
- Applicants: NuFlare Technology, Inc.
- Inventors: Kiyotaka Miyano
- Web page: https://patentgrep.com/patent/US10770481B2

## CPC

- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/8325: {Silicon carbide}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/2926: {Crystal orientations}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3238: {being insulating materials}
- H10P 14/3248: {consisting of two layers}
- H10P 14/3258: {Crystal orientation}
- H10P 14/3408: {Silicon carbide}
- H10P 14/3416: {Nitrides}
- H10P 14/3452: {Microstructure}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/00: Isolation regions in semiconductor bodies between components of integrated devices
- H10W 10/01: {Manufacture or treatment}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3466: {Crystal orientation}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes: a silicon substrate having a first plane with a first plane orientation; a silicon oxide layer provided on a first region of the silicon substrate; a first silicon layer provided on the silicon oxide layer, the first silicon layer having a second plane with a second plane orientation different from the first plane orientation; and a wide-bandgap compound semiconductor layer having a hexagonal crystal structure.

## Claims

### Claim 1

A semiconductor device comprising:
a silicon substrate having a first plane with a first plane orientation;
a silicon oxide layer provided on a first region of the silicon substrate;
a first silicon layer provided on the silicon oxide layer, the first silicon layer having a second plane with a second plane orientation different from the first plane orientation;
a wide-bandgap compound semiconductor layer having a hexagonal crystal structure; and
a second silicon layer provided on a second region of the silicon substrate, the second region being different from the first region,
wherein the wide-bandgap compound semiconductor layer is provided on the first silicon layer,
the first plane orientation is {100},
the second plane orientation is {111} and,
the first silicon layer is undoped.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the wide-bandgap compound semiconductor layer includes a nitride semiconductor.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1,
wherein the wide-bandgap compound semiconductor layer includes silicon carbide.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a first source electrode, a first drain electrode and a first gate electrode provided on the wide-bandgap compound semiconductor layer,
wherein the first gate electrode is provided between the first source electrode and the first drain electrode.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, further comprising:
an element isolation layer provided between the second silicon layer, and the silicon oxide layer, the first silicon layer, and the wide-bandgap compound semiconductor layer.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, further comprising:
an n-type source region provided on the second silicon layer;
an n-type drain region provided on the second silicon layer;
a second source electrode provided on the source region;
a second drain electrode provided on the drain region;
a gate insulating film provided between the second source electrode and the second drain electrode; and
a second gate electrode provided on the gate insulating film,
wherein the second silicon layer is a p type.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a first source electrode, a first drain electrode and a first gate electrode provided on the wide-bandgap compound semiconductor layer;
an n-type source region provided on the second silicon layer;
an n-type drain region provided on the second silicon layer;
a second source electrode provided on the source region;
a second drain electrode provided on the drain region;
a gate insulating film provided between the second source electrode and the second drain electrode; and
a second gate electrode provided on the gate insulating film,
wherein the second silicon layer is a p type,
the first gate electrode is provided between the first source electrode and the first drain electrode,
the first gate electrode is electrically connected to the second source electrode, and
the first source electrode is electrically connected to the second drain electrode.

### Claim 8

A semiconductor device comprising:
a silicon substrate having a first plane with a first plane orientation;
a silicon oxide layer provided on a first region of the silicon substrate;
a first silicon layer provided on the silicon oxide layer, the first silicon layer having a second plane with a second plane orientation different from the first plane orientation; and
a wide-bandgap compound semiconductor layer having a hexagonal crystal structure;
wherein the wide-bandgap compound semiconductor layer is provided on a second region of the silicon substrate, the second region being different from the first region,
the first plane orientation is {111},
the second plane orientation is {100}, and
the second region of the silicon substrate is undoped.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, further comprising:
a first source electrode, a first drain electrode and a first gate electrode provided on the wide-bandgap compound semiconductor layer;
an n-type source region provided on the first silicon layer;
an n-type drain region provided on the first silicon layer;
a second source electrode provided on the source region;
a second drain electrode provided on the drain region;
a gate insulating film provided between the second source electrode and the second drain electrode; and
a second gate electrode provided on the gate insulating film,
wherein the second silicon layer is a p type,
the first gate electrode is provided between the first source electrode and the first drain electrode,
the first gate electrode is electrically connected to the second source electrode, and
the first source electrode is electrically connected to the second drain electrode.

### Claim 10 (depends on 8)

The semiconductor device according to claim 8, further comprising:
an element isolation layer provided between the wide-bandgap compound semiconductor layer, and the silicon oxide layer and the first silicon layer.

### Claim 11 (depends on 8)

The semiconductor device according to claim 8, further comprising:
an n-type source region provided on the first silicon layer;
an n-type drain region provided on the first silicon layer;
a third source electrode provided on the source region;
a third drain electrode provided on the drain region;
a gate insulating film provided between the third source electrode and the third drain electrode; and
a third gate electrode provided on the gate insulating film, wherein the first silicon layer is a p type.