# US 10,770,480 B2 · Systems, methods, and apparatus for enabling high voltage circuits

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- Number: US 10,770,480 B2
- Document ID: US10770480B2
- Status: Granted
- Kind: B2
- Application number: 16/422,648
- Filed: 2019-05-24
- Published: 2019-09-12
- Granted: 2020-09-08
- Earliest claimed: 2016-12-20
- Assignees: pSemi Corporation
- Applicants: pSemi Corporation
- Inventors: Buddhika Abesingha; Simon Edward Willard; Alain Duvallet; Merlin Green; Sivakumar Kumarasamy
- Web page: https://patentgrep.com/patent/US10770480B2

## CPC

- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 86/01: Manufacture or treatment
- H10D 86/411: {characterised by materials, geometry or structure of the substrates}
- H10D 86/60: wherein the TFTs are in active matrices
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Systems, methods and apparatus for coexistence of high voltage and low voltage devices and circuits on a same integrated circuit fabricated in silicon-on-insulator (SOI) technology are described. In particular, techniques for mitigating back gate effects are described, including using of resistive and/or capacitive couplings to control surface potentials at regions of a substrate used for the SOI fabrication proximate the high voltage and low voltage devices and circuits. In one case, an N-type implant is used to provide a high potential differential with respect to a substrate potential.

## Claims

### Claim 1

A silicon on insulator structure comprising:
a high resistivity silicon substrate configured to be coupled to a reference potential;
a buried oxide layer overlying the high resistivity silicon substrate;
a thin silicon layer overlying the buried oxide layer;
a first circuit formed in a first silicon region of the thin silicon layer, the first circuit configured to be coupled to a first potential;
a second circuit formed in a second silicon region of the thin silicon layer, the second circuit configured to be coupled to a second potential different from the first potential, and
at least one through buried oxide contact resistively coupling a local silicon region of one of the first silicon region and the second silicon region to the high resistivity silicon substrate by way of a non-ohmic contact between the through buried oxide contact and the high resistivity silicon substrate,
wherein:
a potential difference between the first potential and the reference potential is equal to or larger than 10 V, and a potential difference between the second potential and the reference potential is equal to or smaller than 5V,
the local silicon region comprises one or more transistors sensitive to a back gate effect, and
the through buried oxide contact is configured to bias a surface potential at a region of the high resistivity silicon substrate proximate the local silicon region to a level substantially equal to one of the first potential and the second potential.

### Claim 2 (depends on 1)

The silicon on insulator structure of claim 1, wherein the high resistivity silicon substrate comprises a trap rich layer.

### Claim 3 (depends on 1)

The silicon on insulator structure of claim 1, wherein a resistance value of the through buried oxide contact is selected to provide a level of the surface potential when the through buried oxide contact is combined with a plurality of elemental resistance paths of the high resistivity silicon substrate.

### Claim 4 (depends on 3)

The silicon on insulator structure of claim 3, wherein:
the first silicon region defines a first surface region of the high resistivity silicon substrate proximate the first silicon region,
the second silicon region defines a second surface region of the high resistivity silicon substrate proximate the second silicon region, and
the plurality of elemental resistance paths comprises resistance paths providing conduction from the first surface region to the second surface region, and resistance paths providing conduction from the first/second surface region to a bottom surface of the high resistivity silicon substrate connected to the reference potential.

### Claim 5 (depends on 1)

The silicon on insulator structure of claim 1, wherein the at least one through buried oxide contact comprises a plurality of through buried oxide contacts configured, in combination, to provide the selected resistance value.

### Claim 6 (depends on 1)

The silicon on insulator structure of claim 1, further comprising an additional at least one through buried oxide contact resistively coupling a local silicon region of the other of the first silicon region and the second silicon region to the high resistivity silicon substrate.

### Claim 7

A silicon on insulator structure comprising:
a high resistivity silicon substrate configured to be coupled to a reference potential;
a buried oxide layer overlying the high resistivity silicon substrate;
a thin silicon layer overlying the buried oxide layer;
a first circuit formed in a first silicon region of the thin silicon layer, the first circuit configured to be coupled to a first potential, the first silicon region forming a first capacitive coupling between the thin silicon layer and the substrate;
a second circuit formed in a second silicon region of the thin silicon layer, the second circuit configured to be coupled to a second potential different from the first potential, the second silicon region forming a second capacitive coupling between the thin silicon layer and the substrate; and
a control structure formed in one or more of the substrate, the buried oxide layer and the thin silicon layer, configured to affect a ratio between values of the first and second capacitive couplings,
wherein:
a potential difference between a high level of the first potential and the reference potential is equal to or larger than 10 V, and a potential difference between high level of the second potential and the reference potential is equal to or smaller than 3 V,
the control structure is configured to control one or both of:
a) a surface potential at a first region of the substrate proximate the first silicon region, and
b) a surface potential at a second region of the substrate proximate the second silicon region.

### Claim 8 (depends on 7)

The silicon on insulator structure according to claim 7, wherein:
the first potential is a switching potential,
the control structure is formed in the thin silicon layer, and
the control structure controls the surface potential at the first/second regions during a transition time of the first switching potential from a low level to the high level, and vice versa, through a combination of the first and second capacitive couplings with a plurality of elemental resistance paths of the high resistivity silicon substrate.

### Claim 9 (depends on 8)

The silicon on insulator structure according to claim 8, wherein the control structure further controls the surface potential at the first/second regions after the transition time of the first switching potential.

### Claim 10 (depends on 8)

The silicon on insulator structure according to claim 8, wherein the control structure comprises regions of the thin silicon layer added to one or both of the first silicon region and the second silicon region.

### Claim 11 (depends on 8)

The silicon on insulator structure according to claim 8, wherein the control structure comprises metal plates formed adjacent to and in contact with one or both of the first silicon region and the second silicon region.

### Claim 12

A method for reducing a back gate effect in a silicon on insulator structure, the method comprising:
forming a first silicon region in a thin silicon layer of the silicon on insulator structure, the first silicon region configured to be coupled to a first voltage having a high level equal to or higher than 10 V, the first silicon region forming a first capacitive coupling between the thin silicon layer and a silicon substrate of the silicon on insulator structure;
forming a second silicon region, isolated from the first silicon region, in the thin silicon layer, the second silicon region configured to be coupled to a second voltage having a high level equal to or lower than 3 V, the second silicon region forming a second capacitive coupling between the thin silicon layer and the substrate;
forming a control structure configured to affect a ratio between values of the first and the second capacitive couplings;
coupling the first voltage to the first silicon region and the second voltage to the second silicon region;
coupling the substrate to a reference potential;
based on the forming and the coupling, controlling one or both of:
i) a surface potential at a first region of the substrate proximate the first silicon region, and
ii) a surface potential at a second region of the substrate proximate the second silicon region, and
based on the controlling, reducing the back gate effect in one or both of the first silicon region and the second silicon region,
wherein the substrate is a high resistivity silicon substrate.

### Claim 13 (depends on 12)

The method according to claim 12, wherein:
the control structure controls the surface potential at the first/second regions during a transition time of the first voltage from a low level to the high level, and vice versa, through a combination of the first and second capacitive couplings with a plurality of elemental resistance paths of the high resistivity silicon substrate.

### Claim 14 (depends on 13)

The method according to claim 13, wherein the control structure further controls the surface potential at the first/second regions after the transition time of the first voltage.

### Claim 15

A method for reducing a back gate effect in a silicon on insulator structure, the method comprising:
forming a first silicon region in a thin silicon layer of the structure, the first silicon region configured to be coupled to a first voltage having a high level equal to or higher than 10 V;
forming a second silicon region, isolated from the first silicon region, in the thin silicon layer, the second silicon region configured to be coupled to a second voltage having a high level equal to or lower than 5 V;
forming a control structure configured to affect a coupling between the thin silicon layer and a silicon substrate of the structure;
coupling the first voltage to the first silicon region and the second voltage to the second silicon region;
coupling the substrate to a reference potential;
based on the forming and the coupling, controlling one or both of:
iii) a potential at a first surface region of the substrate proximate the first silicon region, and
iv) a potential at a second surface region of the substrate proximate the second silicon region, and
based on the controlling, reducing the back gate effect in one or both of the first silicon region and the second silicon region,
wherein the substrate is a high resistivity silicon substrate,
wherein the first and second voltages are DC or switching voltages,
wherein the control structure resistively couples, through the buried oxide layer, a local silicon region of one of the first silicon region and the second silicon region to the substrate by way of a non-ohmic contact between a through buried oxide layer contact and the high resistivity silicon substrate, and
wherein the control structure controls the potential at the first/second surface regions during a steady state of the first voltage through a combination of the resistive coupling with a plurality of elemental resistance paths of the high resistivity silicon substrate.