Three-dimensional device and method of forming the same

A method for manufacturing a semiconductor device, comprising:

• forming a semiconductor structure, the semiconductor structure including a first channel structure, a second channel structure, and a plurality of power rails buried in a substrate, the plurality of power rails being positioned below the first channel structure to form a stair-case configuration, the second channel structure being formed over the first channel structure, the first and second channel structures extending along a length direction of the plurality of power rails;
• forming a plurality of first sources/drains, the plurality of first sources/drains surrounding the first channel structure, and being embedded in a first dielectric layer;
• forming a plurality of first source/drain (S/D) contacts, each of the plurality of first S/D contacts being formed over a respective first source/drain, and having a bar shape with a top portion, a bottom portion and side portions so that the bottom portion covers the respective first source/drain;
• forming a plurality of first dielectric caps over the plurality of first S/D contacts, each of the plurality of first dielectric caps being positioned over a respective first S/D contact to cover the top portion and at least a part of the side portions of the respective first S/D contact;
• forming a plurality of second sources/drains, the plurality of second sources/drains being positioned over the plurality of first sources/drains and surrounding the second channel structure, and being embedded in a second dielectric layer;
• forming a plurality of second source/drain (S/D) contacts, each of the plurality of second S/D contacts being formed over a respective second source/drain, and having a bar shape with a top portion, a bottom portion and side portions so that the bottom portion covers the respective second source/drain, the plurality of second S/D contacts being staggered over the plurality of first S/D contacts to form a stair-case configuration;
• and
• forming a plurality of second dielectric caps over the plurality of second S/D contacts, each of the plurality of second dielectric caps being positioned over a respective second S/D contact to cover the top portion and at least a part of the side portions of the respective second S/D contact.

A semiconductor device, comprising:

• a substrate;
• a plurality of power rails buried in the substrate;
• a plurality of first sources/drains formed over the plurality of power rails so as to form a stair-case configuration;
• a plurality of first source/drain (S/D) contacts formed over the plurality of first sources/drains, each of the plurality of first S/D contacts being formed over a respective first source/drain, and having a bar shape with a top portion, a bottom portion and side portions so that the bottom portion covers the respective first source/drain;
• a plurality of first dielectric caps formed over the plurality of first S/D contacts, each of the plurality of first dielectric caps being positioned over a respective first S/D contact to cover the top portion and at least a part of the side portions of the respective first S/D contact so as to separate the respective first S/D contact from at least one of an adjacent first S/D contact, an adjacent via-to-drain structure, an adjacent first via-to-rail structure, and an adjacent second via-to-rail structure;
• a plurality of second sources/drains formed over the plurality of first sources/drains to form a stair-case configuration;
• a plurality of second source/drain (S/D) contacts formed over the plurality of second sources/drains, each of the plurality of second S/D contacts being formed over a respective second source/drain, and having a bar shape with a top portion, a bottom portion and side portions so that the bottom portion covers the respective second source/drain, the plurality of second S/D contacts being staggered over the plurality of first S/D contacts to form a stair-case configuration;
• and
• a plurality of second dielectric caps formed over the plurality of second S/D contacts, each of the plurality of second dielectric caps being positioned over a respective second S/D contact to cover the top portion and at least a part of the side portions of the respective second S/D contact so as to separate the respective second S/D contact from at least one of an adjacent second S/D contact, an adjacent via-to-drain structure, and an adjacent second via-to-rail structure,
• wherein at least one of the plurality of first S/D contacts being connected to a first power rail of the plurality of power rails through a first via-to-rail structure, and at least one of the plurality of second S/D contacts being connected to a second power rail of the plurality of power rails through a second via-to-rail structure.