# US 10,770,478 B1 · Methods for forming three-dimensional memory device having bent backside word lines

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- Number: US 10,770,478 B1
- Document ID: US10770478B1
- Status: Granted
- Kind: B1
- Application number: 16/453,974
- Filed: 2019-06-26
- Granted: 2020-09-08
- Earliest claimed: 2019-04-30
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Li Hong Xiao
- Web page: https://patentgrep.com/patent/US10770478B1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 64/0113: {the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3456: {Polycrystalline}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/264: {by chemical means}
- H10P 50/283: {by chemical means}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 46/201: {located on the periphery of wafers, e.g. orientation notches or lot numbers}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of methods for forming three-dimensional (3D) memory devices having bent backside word lines are disclosed. In an example, a method for forming a 3D memory device is disclosed. A notch is formed on at least one edge of a substrate. A semiconductor layer above the substrate and extending laterally beyond the at least one edge of the substrate is formed to cover the notch. A plurality of interleaved conductive layers and dielectric layers are formed along a front side and the at least one edge of the semiconductor layer and along a top surface, a side surface, and a bottom surface of the notch. A portion of the substrate is removed to expose the interleaved conductive layers and dielectric layers below the semiconductor layer.

## Claims

### Claim 1

A method for forming a three-dimensional (3D) memory device, comprising:
forming a notch on at least one edge of a substrate;
forming a semiconductor layer above the substrate and extending laterally beyond the at least one edge of the substrate to cover the notch;
forming a plurality of interleaved conductive layers and dielectric layers along a front side and the at least one edge of the semiconductor layer and along a top surface, a side surface, and a bottom surface of the notch; and
removing a portion of the substrate to expose the interleaved conductive layers and dielectric layers below the semiconductor layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the notch comprises forming two notches on both edges of the substrate, respectively.

### Claim 3 (depends on 1)

The method of claim 1, wherein a depth of the notch is greater than twice of a combined thickness of the conductive layer and the dielectric layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the semiconductor layer comprises:
filling the notch with a notch sacrificial layer;
depositing the semiconductor layer above the substrate and the notch sacrificial layer; and
removing the notch sacrificial layer in the notch.

### Claim 5 (depends on 1)

The method of claim 1, wherein a thickness of the semiconductor layer is not greater than 1 μm.

### Claim 6 (depends on 1)

The method of claim 1, wherein the semiconductor layer comprises polysilicon.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the plurality of interleaved conductive layers and dielectric layers comprises alternatingly depositing the plurality of conductive layers and dielectric layers using atomic layer deposition (ALD).

### Claim 8 (depends on 7)

The method of claim 7, wherein each of the conductive layers comprises doped polysilicon, and each of the dielectric layers comprises silicon oxide.

### Claim 9 (depends on 1)

The method of claim 1, wherein forming the plurality of interleaved conductive layers and dielectric layers comprises:
alternatingly depositing a plurality of sacrificial layers and the dielectric layers using ALD; and
replacing the sacrificial layers with the conductive layers.

### Claim 10 (depends on 9)

The method of claim 9, wherein each of the sacrificial layers comprises silicon nitride, each of the dielectric layers comprises silicon oxide, and each of the conductive layers comprises a metal.

### Claim 11 (depends on 1)

The method of claim 1, wherein removing the portion of the substrate comprises:
depositing an etch stop layer over the interleaved conductive layers and dielectric layers; and
thinning the substrate until being stopped by the etch stop layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein the etch stop layer comprises polysilicon.

### Claim 13 (depends on 1)

The method of claim 1, wherein the portion of the substrate is removed, such that the bottom surface and a portion of the side surface of the notch are removed.

### Claim 14

A method for forming a three-dimensional (3D) memory device, comprising:
forming a notch on at least one edge of a substrate;
forming a semiconductor layer above the substrate and extending laterally beyond the at least one edge of the substrate to cover the notch;
alternatingly depositing a plurality of sacrificial layers and dielectric layers along a front side and the at least one edge of the semiconductor layer and along a top surface, a side surface, and a bottom surface of the notch;
removing a portion of the substrate to expose the interleaved sacrificial layers and dielectric layers below the semiconductor layer; and
replacing the sacrificial layers with a plurality of conductive layers.

### Claim 15 (depends on 14)

The method of claim 14, wherein the plurality of sacrificial layers and dielectric layers are alternatingly deposited using atomic layer deposition (ALD).

### Claim 16 (depends on 14)

The method of claim 14, wherein each of the sacrificial layers comprises silicon nitride, each of the dielectric layers comprises silicon oxide, and each of the conductive layers comprises a metal.

### Claim 17 (depends on 14)

The method of claim 14, wherein removing the portion of the substrate comprises:
depositing an etch stop layer over the interleaved sacrificial layers and dielectric layers; and
thinning the substrate until being stopped by the etch stop layer.

### Claim 18

A method for forming a three-dimensional (3D) memory device, comprising:
forming a notch on at least one edge of a substrate;
forming a semiconductor layer above the substrate and extending laterally beyond the at least one edge of the substrate to cover the notch;
alternatingly depositing a plurality of conductive layers and dielectric layers along a front side and the at least one edge of the semiconductor layer and along a top surface, a side surface, and a bottom surface of the notch; and
removing a portion of the substrate to expose the interleaved conductive layers and dielectric layers below the semiconductor layer.

### Claim 19 (depends on 18)

The method of claim 18, wherein the plurality of conductive layers and dielectric layers are alternatingly deposited using atomic layer deposition (ALD).

### Claim 20 (depends on 18)

The method of claim 18, wherein each of the conductive layers comprises doped polysilicon, and each of the dielectric layers comprises silicon oxide.