# US 10,770,477 B2 · Vertical semiconductor devices

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- Number: US 10,770,477 B2
- Document ID: US10770477B2
- Status: Granted
- Kind: B2
- Application number: 16/401,667
- Filed: 2019-05-02
- Published: 2020-05-07
- Granted: 2020-09-08
- Earliest claimed: 2018-11-07
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Bong-Yong Lee; Tae-Hun Kim; Min-Kyung Bae; Myung-Hun Woo
- Web page: https://patentgrep.com/patent/US10770477B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/10: characterised by the top-view layout
- H10P 50/283: {by chemical means}
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A vertical semiconductor device includes a plurality of channel connection patterns, a lower insulation layer, a supporting layer, a stacked structure, and a channel structure. The channel connection patterns, on which the lower insulation layer is formed, contact a substrate. The supporting layer is formed on the lower insulation layer to be spaced apart from the channel connection patterns, and includes polysilicon doped with impurities. The stacked structure is formed on the supporting layer, and includes insulation layers and gate electrodes to form a memory cell string. The channel structure passes through the stacked structure, the supporting layer and the lower insulation layer, and includes a charge storage structure and a channel which contacts the channel connection patterns. The charge storage structure and the channel face the gate electrodes and the supporting layer. The supporting layer serves as a gate of a gate induced drain leakage (GIDL) transistor.

## Claims

### Claim 1

A vertical semiconductor device, comprising:
a plurality of channel connection patterns contacting an upper surface of a substrate;
a lower insulation layer formed on the channel connection patterns and in a space between the channel connection patterns;
a supporting layer formed on the lower insulation layer to be spaced apart from the channel connection patterns, the supporting layer comprising polysilicon doped with impurities;
a stacked structure formed on the supporting layer, the stacked structure in which insulation layers and gate electrodes are stacked; and
a channel structure passing through the stacked structure, the supporting layer and the lower insulation layer, and extending to an upper portion of the substrate, the channel structure comprising a charge storage structure and a channel,
wherein the channel contacts the channel connection pattern, and
wherein the charge storage structure and the channel are disposed to face the gate electrodes and the supporting layer, and the supporting layer is configured to function a gate of a gate induced drain leakage (GIDL) transistor.

### Claim 2 (depends on 1)

The vertical semiconductor device of claim 1, wherein the gate electrodes formed above the supporting layer comprises a metal, and
wherein the supporting layer is an only layer serving as the gate of the GIDL transistor in the vertical semiconductor device.

### Claim 3 (depends on 1)

The vertical semiconductor device of claim 1, wherein the channel connection pattern comprises polysilicon doped with impurities.

### Claim 4 (depends on 1)

The vertical semiconductor device of claim 1, wherein the channel structure is formed in a channel hole passing through the stacked structure, the supporting layer and the lower insulation layer, and extending to the upper portion of the substrate,
wherein the charge storage structure is formed on an upper portion of a sidewall of the channel hole disposed at a level higher than the channel connection pattern, and
wherein the channel contacts the charge storage structure and the channel connection pattern, and has a cylindrical shape.

### Claim 5 (depends on 4)

The vertical semiconductor device of claim 4, wherein a bottom of an inner space of the channel having the cylindrical shape is positioned at a level between an upper surface of the supporting layer and a bottom of a lowermost gate electrode among the gate electrodes.

### Claim 6 (depends on 1)

The vertical semiconductor device of claim 1, wherein the channel at a level below a lowermost gate electrode among the gate electrodes is doped with impurities, and
wherein the channel at a level at or above the lowermost gate electrode is not or less doped with the impurities compared to the channel at the level below the lowermost gate electrode.

### Claim 7 (depends on 1)

The vertical semiconductor device of claim 1, further comprising:
a common source line passing through the stacked structure, the supporting layer and the lower insulation layer, and contacting a portion of the substrate; and
a spacer comprising an insulation material, the spacer surrounding a sidewall of the common source line.

### Claim 8 (depends on 7)

The vertical semiconductor device of claim 7, wherein the supporting layer contacts the spacer on the sidewall of the common source line, and
wherein the supporting layer and the common source line are electrically isolated from each other by the spacer.

### Claim 9 (depends on 7)

The vertical semiconductor device of claim 7, wherein an upper surface of the supporting layer comprises a recess, and the common source line passing through the recess.

### Claim 10 (depends on 1)

The vertical semiconductor device of claim 1, further comprising a dummy channel structure passing through the stacked structure and the supporting layer, and extending to an upper portion of the substrate,
wherein the dummy channel structure comprises a charge storage structure and a channel that is not electrically connected to the channel connection pattern.

### Claim 11

A vertical semiconductor device, comprising:
a plurality of channel connection patterns contacting an upper surface of a substrate;
a lower insulation layer formed on the channel connection patterns and a space between the channel connection patterns;
a supporting layer formed on the lower insulation layer to be spaced apart from the channel connection patterns, the supporting layer comprising polysilicon doped with impurities;
a stacked structure formed on the supporting layer, the stacked structure in which insulation layers and gate electrodes are stacked; and
a channel structure passing through the stacked structure, the supporting layer and the lower insulation layer, and extending to an upper portion of the substrate, the channel structure comprising a charge storage structure and a channel, the channel contacting the channel connection pattern and having a cylindrical shape,
wherein the charge storage structure and the channel are disposed to face the gate electrodes and the supporting layer, and
wherein a width of the channel at a level below an upper surface of the supporting layer is greater than a width of the channel at a level above the upper surface of the supporting layer.

### Claim 12 (depends on 11)

The vertical semiconductor device of claim 11, wherein the gate electrodes formed above the supporting layer comprises a metal, and
wherein the supporting layer is configured to function as a gate induced drain leakage (GIDL) transistor.

### Claim 13 (depends on 11)

The vertical semiconductor device of claim 11, wherein a bottom of an inner space of the channel having the cylindrical shape is positioned at a level between an upper surface of the supporting layer and a bottom of a lowermost gate electrode.

### Claim 14 (depends on 11)

The vertical semiconductor device of claim 11, wherein the channel at a level below a lowermost gate electrode among the gate electrodes is doped with impurities.

### Claim 15

A vertical semiconductor device, comprising:
a lower gate layer formed above a substrate, the lower gate layer being spaced apart from the substrate, and the lower gate layer comprising polysilicon doped with impurities;
a stacked structure formed on the lower gate layer, the stacked structure in which insulation layers and gate electrodes are stacked to form a memory cell string, and the gate electrodes comprising a metal; and
a channel structure passing through the stacked structure and the lower gate layer and extending to an upper portion of the substrate, the channel structure comprising a charge storage structure and a channel having a cylindrical shape,
wherein the charge storage structure and the channel are disposed to face the gate electrodes and the lower gate layer, and
wherein a width of the channel at a level below an upper surface of the lower gate layer is greater than a width of the channel at a level above the upper surface of the lower gate layer.

### Claim 16 (depends on 15)

The vertical semiconductor device of claim 15, the channel at a level below a lowermost gate electrode among the gate electrodes is selectively doped with impurities.

### Claim 17 (depends on 15)

The vertical semiconductor device of claim 15, further comprising:
a channel connection patterns formed on the substrate, the channel connection patterns contacting an upper surface of the substrate and the channel, the channel connection patterns being spaced apart from the lower gate layer; and
a lower insulation layer formed between the channel connection patterns and the lower gate layer.

### Claim 18 (depends on 15)

The vertical semiconductor device of claim 15, wherein the lower gate layer is configured to structurally support the stacked structure, and comprises a material having an etch selectively with respect to silicon oxide and silicon nitride.

### Claim 19 (depends on 15)

The vertical semiconductor device of claim 15, wherein the lower gate layer is configured to function as a gate induced drain leakage (GIDL) transistor, and
wherein a thickness of the lower gate layer in a vertical direction may be substantially equal to a channel length of the GIDL transistor.

### Claim 20 (depends on 19)

The vertical semiconductor device of claim 19, the memory cell string comprise a ground selection transistor, a cell transistor and a cell selection transistor.