# US 10,770,474 B2 · Manufacturing method of semiconductor device

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- Number: US 10,770,474 B2
- Document ID: US10770474B2
- Status: Granted
- Kind: B2
- Application number: 16/148,416
- Filed: 2018-10-01
- Published: 2019-10-17
- Granted: 2020-09-08
- Earliest claimed: 2018-04-12
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Sang Hyon Kwak; Duk Eui Lee; Nam Gyu Kim
- Web page: https://patentgrep.com/patent/US10770474B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/10: characterised by the top-view layout
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/037: {comprising charge-trapping insulators}
- H10P 14/6304: {Formation by oxidation, e.g. oxidation of the substrate}
- H10P 50/283: {by chemical means}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A manufacturing method of a semiconductor device includes: forming pillars in a first region of a stack structure in which interlayer insulating layers and sacrificial insulating layers are alternately stacked; forming a slit in a second region of the stack structure; and removing the sacrificial insulating layers in the first region. In the removing of the sacrificial insulating layers in the first region, a portion of each of the sacrificial insulating layers, which is adjacent to the slit, and a portion of each of the sacrificial insulating layers, which is disposed between the pillars, may be removed using different etching materials.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming a stack structure including a first region and a second region by alternately stacking interlayer insulating layers and sacrificial insulating layers on a lower structure;
forming pillars penetrating the first region of the stack structure;
forming a slit penetrating the second region of the stack structure;
forming first openings between the interlayer insulating layers by removing only a portion of each of the sacrificial insulating layers remaining between a slit-side pillar adjacent to the slit among the pillars and the slit, wherein the forming of the first openings is performed through dry etching using a first etching material introduced through the slit; and
forming second openings between the interlayer insulating layers by removing remaining portions of the sacrificial insulating layers which were not removed while forming the first openings between the interlayer insulating layers, wherein the forming of the second openings is performed through wet etching using a second etching material introduced through the first openings.

### Claim 2 (depends on 1)

The method of claim 1, further comprising filling the first and second openings with conductive patterns.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first etching material has a first etching selection ratio at which it rapidly etches the sacrificial insulating layers as compared with the interlayer insulating layers, and
the second etching material has a second etching selection ratio at which it rapidly etches the sacrificial insulating layers as compared with the interlayer insulating layers,
wherein the first etching selection ratio is lower than the second etching selection ratio.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first etching material is in a gaseous state, and
the second etching material is in a soluble state.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first etching material includes at least one of a gas in which nitrogen trifluoride (NF3) and oxygen (O2) are mixed, a gas in which hydrogen fluoride (HF) and oxygen (O2) are mixed, and a chlorotrifluoride (CIF3) gas.

### Claim 6 (depends on 1)

The method of claim 1, wherein the second etching material includes a phosphoric acid.

### Claim 7 (depends on 1)

The method of claim 1, wherein the width of each of the first openings in the direction in which the interlayer insulating layers and the sacrificial insulating layers are stacked increases when approaching the slit.

### Claim 8 (depends on 1)

The method of claim 1, wherein the lower structure includes a semiconductor substrate, a conductive layer or a doped silicon layer.

### Claim 9 (depends on 1)

The method of claim 1, further comprising, before the first etching material is introduced, forming a protective layer by oxidizing the lower structure exposed through the slit.

### Claim 10 (depends on 1)

The method of claim 1, wherein each of the pillars includes:
a vertical channel extending in the direction in which the interlayer insulating layers and the sacrificial insulating layers are stacked;
a tunnel insulating layer surrounding the vertical channel;
a data storage layer surrounding the tunnel insulating layer; and
a blocking insulating layer surrounding the data storage layer.

### Claim 11

A method of manufacturing a semiconductor device, the method comprising:
forming a stack structure by alternately stacking interlayer insulating layers and sacrificial insulating layers on a lower structure, the stack structure including first regions spaced apart from one another and a second region disposed between the first regions;
forming holes penetrating each of the first regions of the stack structure;
forming pillars filling in the holes, the pillars being divided into first and second pillar groups by the second region, each of the first and second pillar groups including a center pillar and a slit-side pillar;
forming a slit penetrating the second region to a depth to expose the lower structure;
forming a protective layer on the lower structure which is exposed through the slit;
removing only a portion of each of the sacrificial insulating layers which remains between the slit and the slit-side pillar through a first selective etching process by introducing a first etching material through the slit to form first openings between adjacent interlayer insulating layers; and
performing a second selective etching process using a second etching material that is different from the first etching material for removing remaining portions of the sacrificial insulating layers adjacent to the slit which were not removed with the first selective etching process, and the sacrificial insulating layers between the pillars.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first etching material includes at least one of a gas in which nitrogen trifluoride (NF3) and oxygen (O2) are mixed, a gas in which hydrogen fluoride (HF) and oxygen (O2) are mixed, and a chlorotrifluoride (CIF3) gas, and
wherein the second etching material is a solution including a phosphoric acid.

### Claim 13 (depends on 11)

The method of claim 11, further comprising filling the first and second openings with conductive patterns.

### Claim 14 (depends on 11)

The method of claim 11, wherein the first etching material has a first etching selection ratio at which it rapidly etches the sacrificial insulating layers as compared with the interlayer insulating layers, and
the second etching material has a second etching selection ratio at which it rapidly etches the sacrificial insulating layers as compared with the interlayer insulating layers,
wherein the first etching selection ratio is lower than the second etching selection ratio.

### Claim 15 (depends on 11)

The method of claim 11, wherein the first selective etching process is performed through dry etching using the first etching material in a gaseous state, and
the second selective etching process is performed through wet etching using the second etching material in a soluble state.

### Claim 16 (depends on 11)

The method of claim 11, wherein the width of each of the first openings in the direction in which the interlayer insulating layers and the sacrificial insulating layers are stacked increases in a direction approaching the slit.

### Claim 17 (depends on 11)

The method of claim 11, wherein the lower structure includes a semiconductor substrate, a conductive layer or a doped silicon layer.

### Claim 18 (depends on 11)

The method of claim 11, wherein the protective layer is formed by oxidizing the lower structure exposed through the slit.

### Claim 19 (depends on 11)

The method of claim 11, wherein each of the pillars includes:
a vertical channel extending in the direction in which the interlayer insulating layers and the sacrificial insulating layers are stacked;
a tunnel insulating layer surrounding the vertical channel;
a data storage layer surrounding the tunnel insulating layer; and
a blocking insulating layer surrounding the data storage layer.