# US 10,770,467 B2 · Semiconductor device and method for fabricating the same

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- Number: US 10,770,467 B2
- Document ID: US10770467B2
- Status: Granted
- Kind: B2
- Application number: 16/196,197
- Filed: 2018-11-20
- Published: 2019-03-21
- Granted: 2020-09-08
- Earliest claimed: 2014-09-03
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Soo-Yeon Jeong; Dong-Gu Yi; Tae-Jong Lee; Jae-Po Lim
- Web page: https://patentgrep.com/patent/US10770467B2

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- H10B 10/18: {Peripheral circuit regions}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/118: {Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0158: {the components including FinFETs}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Provided are a semiconductor device and a method for fabricating the same. The semiconductor device comprises a first fin type active pattern formed on a substrate and extending in a first direction and including first to third parts. At least one dimension of the third part measuring less than the corresponding dimension of the first part. A gate electrode extending in a second direction different from the first direction is at least partially formed on the first part of the fin type active pattern. A first source/drain is formed on the third part of the fin type active pattern.

## Claims

### Claim 1

A method for fabricating a semiconductor device, the method comprising:
forming a fin type active pattern defined by a field insulation layer, extending in a first direction, including first to third parts sequentially arranged in the first direction and upwardly protruding from a top surface of the field insulation layer;
forming a dummy gate electrode extending in a second direction different from the first direction and crossing the fin type active pattern on the first part;
trimming the second and third parts upwardly protruding from the top surface of the field insulation layer using the dummy gate electrode as a mask;
forming a gate spacer formed on the second part and sidewalls of the dummy gate electrode after the trimming the second and third parts;
forming a recess in the third part using the dummy gate electrode as a mask; and
forming a source/drain filling the recess on the third part,
wherein the second and third parts upwardly protrude from the top surface of the field insulation layer between the forming the gate spacer and after the trimming the second and third parts.

### Claim 2 (depends on 1)

The method of claim 1, wherein the trimming reduces heights and widths of the second part and the third part.

### Claim 3 (depends on 1)

The method of claim 1, wherein the forming the recess includes covering sidewalls of the third part with field insulation layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first part, the second part and the third part have the same width at a boundary between the field insulation layer and the fin type active pattern.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first part has a greater width than the second part at a first height from a top surface of the field insulation layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein a top surface of the second part and a top surface of the first part have discontinuous profiles, and opposite sidewalls of the second part facing each other in the second direction and opposite sidewalls of the first part facing each other in the second direction have discontinuous profiles.

### Claim 7 (depends on 6)

The method of claim 6, wherein the first part includes connecting sidewalls, and
wherein the connecting sidewalls connect the top surface of the first part and the top surface of the second part and connect the opposite sidewalls of the first part and the opposite sidewalls of the second part.

### Claim 8 (depends on 7)

The method of claim 7, wherein the gate spacer overlaps the connecting sidewalls.

### Claim 9 (depends on 1)

The method of claim 1, further comprising forming a fin spacer on the sidewalls of the third part upwardly protruding from the top surface of the field insulation layer.

### Claim 10

A method for fabricating a semiconductor device, the method comprising:
forming a fin type active pattern defined by a field insulation layer, extending in a first direction, including first to third parts sequentially arranged in the first direction and upwardly protruding from a top surface of the field insulation layer;
trimming the fin type active pattern upwardly protruding from the top surface of the field insulation layer;
forming a dummy gate electrode extending in a second direction different from the first direction and crossing the fin type active pattern on a trimmed first part;
forming a gate spacer formed on sidewalls of the dummy gate electrode and a trimmed second part;
forming a recess in a trimmed third part using the dummy gate electrode as a mask; and
forming a source/drain filling the recess on the trimmed third part
wherein the trimmed first part has a greater width than the trimmed second part at a first height from the top surface of the field insulation layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein the trimming reduces heights and widths of the second part and the third part.

### Claim 12 (depends on 10)

The method of claim 10, wherein the source/drain is epitaxially grown, using the fin type active pattern as a seed.

### Claim 13 (depends on 10)

The method of claim 10, wherein the trimmed first part, the trimmed second part and the trimmed third part have the same width at a boundary between the field insulation layer and the fin type active pattern.