# US 10,770,465 B1 · Method used in forming integrated circuitry

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- Number: US 10,770,465 B1
- Document ID: US10770465B1
- Status: Granted
- Kind: B1
- Application number: 16/399,348
- Filed: 2019-04-30
- Granted: 2020-09-08
- Earliest claimed: 2019-04-30
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Byeung Chul Kim; Richard J. Hill; John A. Smythe; Gurtej S. Sandhu
- Web page: https://patentgrep.com/patent/US10770465B1

## CPC

- H10B 12/482: {Bit lines}
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method used in forming integrated circuitry comprises forming a substrate comprising a conductive line structure comprising opposing longitudinal sides individually comprising a sacrificial material that is laterally between insulator material. The sacrificial material comprises metal oxide. At least some of the sacrificial material is removed to form an upwardly-open void space laterally between the insulator material on the opposing longitudinal sides of the conductive line structure. The void space is covered with insulating material to leave a sealed void space beneath the insulating material on the opposing longitudinal sides of the conductive line structure. Other embodiments are disclosed.

## Claims

### Claim 1

A method used in forming integrated circuitry, comprising:
forming a substrate comprising a conductive line structure comprising opposing longitudinal sides individually comprising a sacrificial material that is laterally between insulator material, the sacrificial material comprising metal oxide;
removing at least some of the sacrificial material to form an upwardly-open void space laterally between the insulator material on the opposing longitudinal sides of the conductive line structure; and
covering the void space with insulating material to leave a sealed void space beneath the insulating material on the opposing longitudinal sides of the conductive line structure.

### Claim 2 (depends on 1)

The method of claim 1 wherein the metal of the metal oxide comprises at least one of Sn, Ga, Ge, Se, In, Te, Bi, V, Sr, Nb, Ta, Mg, P, W, La, and Ba.

### Claim 3 (depends on 1)

The method of claim 1 wherein the sacrificial material consists essentially of the metal oxide.

### Claim 4 (depends on 1)

The method of claim 1 wherein the sacrificial material consists of the metal oxide.

### Claim 5 (depends on 1)

The method of claim 1 wherein the insulator material is of the same composition on both sides of the sacrificial material.

### Claim 6 (depends on 1)

The method of claim 1 wherein the sacrificial material is conductive.

### Claim 7 (depends on 1)

The method of claim 1 wherein said removing is of all of the sacrificial material that is laterally between the insulator.

### Claim 8 (depends on 2)

The method of claim 2 wherein the metal of the metal oxide comprises at least two of Sn, Ga, Ge, Se, In, Te, Bi, V, Sr, Nb, Ta, Mg, P, W, La, and Ba.

### Claim 9

A method used in forming integrated circuitry, comprising:
forming a substrate comprising conductive line structures individually comprising opposing longitudinal sides individually comprising sacrificial material that is laterally between insulator material, the sacrificial material comprising metal oxide;
forming conductive vias laterally between and spaced longitudinally along the conductive line structures;
forming conductive material directly above and directly against the conductive vias and directly above the conductive line structures;
etching through the conductive material to the conductive line structures to expose the sacrificial material;
removing at least some of the sacrificial material to form an upwardly-open void space laterally between the insulator material on the opposing longitudinal sides of individual of the conductive line structures; and
covering the void space with insulating material to leave a sealed void space beneath the insulating material on the opposing longitudinal sides of the individual conductive line structures.

### Claim 10 (depends on 9)

The method of claim 9 wherein the integrated circuitry comprises memory circuitry and the conductive line structures are digitline structures of the memory circuitry.

### Claim 11 (depends on 9)

The method of claim 9 wherein the etching forms islands of the conductive material that are individually directly electrically coupled to individual of the conductive vias.

### Claim 12 (depends on 9)

The method of claim 9 wherein said removing is of all of the sacrificial material that is laterally between the insulator material.

### Claim 13 (depends on 9)

The method of claim 9 wherein the etching is into the conductive line structure.

### Claim 14 (depends on 11)

The method of claim 11 comprising forming a plurality of a storage elements that are individually directly electrically coupled to individual of the islands.

### Claim 15 (depends on 13)

The method of claim 13 wherein the etching is into an uppermost portion of the conductive line structure.

### Claim 16 (depends on 13)

The method of claim 13 wherein the etching is into the insulator material of the conductive line structure.

### Claim 17 (depends on 13)

The method of claim 13 wherein the etching is into the sacrificial material of the conductive line structure.

### Claim 18 (depends on 13)

The method of claim 13 wherein,
the etching is into the insulator material of the conductive line structure; and
the etching is into the sacrificial material of the conductive line structure.

### Claim 19

A method used in forming memory circuitry, comprising:
forming transistors individually comprising:
a pair of source/drain regions;
a channel region between the pair of source/drain regions;
a conductive gate operatively proximate the channel region; and
a gate insulator between the conductive gate and the channel region;
forming digitline structures that are individually directly electrically coupled to one of the source/drain regions of multiple of the individual pairs of source/drain regions, the digitline structures individually comprising opposing longitudinal sides individually comprising a sacrificial material that is laterally between insulator material, the sacrificial material comprising metal oxide;
forming conductive vias laterally between and spaced longitudinally along the digitline structures, individual of the conductive vias being directly electrically coupled to one of the other source/drain regions in the individual pairs of source/drain regions;
forming conductive material of a redistribution layer directly above and directly against the conductive vias and directly above the digitline structures;
etching through the conductive material to the digitline structures to expose the sacrificial material and to pattern the redistribution layer into separated islands that are individually directly electrically coupled to the individual conductive vias;
removing at least some of the sacrificial material to form an upwardly-open void space laterally between the insulator material on the opposing longitudinal sides of individual of the digitline structures;
covering the void space with insulating material to leave a sealed void space beneath the insulating material on the opposing longitudinal sides of the individual digitline line structures; and
forming a plurality of a storage elements that are individually directly electrically coupled to individual of the islands.

### Claim 20 (depends on 19)

The method of claim 19 comprising forming the memory circuitry to comprise DRAM.

### Claim 21 (depends on 19)

The method of claim 19 comprising forming the transistors in pairs, the one source/drain region of the respective pairs of source/drain regions in individual of the pairs of the transistors that is directly electrically coupled to one of the digitline structures being laterally between the conductive gates in and being shared by the individual pairs of transistors, the others of the source/drain regions of the pair of source/drain regions not being shared in the individual pairs of transistors.

### Claim 22 (depends on 21)

The method of claim 21 wherein the pairs of transistors comprise pairs of recessed access devices individually comprising:
the conductive gate being in a trench in semiconductive material;
the gate insulator being along sidewalls and a base of the trench between the conductive gate and the semiconductive material;
the pair of source/drain regions being in upper portions of the semiconductive material on opposing sides of the trench; and
the channel region being in the semiconductive material below the pair of source/drain regions along the trench sidewalls and around the trench base.

### Claim 23 (depends on 22)

The method of claim 22 comprising forming the memory circuitry to comprise DRAM.

### Claim 24 (depends on 19)

The method of claim 19 wherein the void space along each of the opposing longitudinal sides has cyclically varying height longitudinally along the digitline structure.

### Claim 25 (depends on 24)

The method of claim 24 wherein the cyclically varying height has a repeating cycle of two heights.

### Claim 26 (depends on 25)

The method of claim 25 wherein a shorter of the two heights is longitudinally longer along the digitline structure than is a taller of the two heights.

### Claim 27 (depends on 24)

The method of claim 24 wherein the cyclically varying height of the opposing void spaces has a repeating cycle that is the same as one another.

### Claim 28 (depends on 27)

The method of claim 27 wherein the same repeating cycle of the opposing void spaces are longitudinally offset relative one another.

### Claim 29 (depends on 28)

The method of claim 28 wherein the repeating cycle is of two heights.

### Claim 30

A method used in forming integrated circuitry, comprising:
forming a sacrificial material that is laterally between insulator material, the sacrificial material comprising metal oxide;
removing at least some of the sacrificial material to form an upwardly-open void space laterally between the insulator material; and
covering the void space with insulating material to leave a sealed void space beneath the insulating material.

### Claim 31 (depends on 30)

The method of claim 30 wherein the metal of the metal oxide comprises at least one of Sn, Ga, Ge, Se, In, Te, Bi, V, Sr, Nb, Ta, Mg, P, W, La, and Ba.

### Claim 32 (depends on 30)

The method of claim 30 wherein the insulator material is of the same composition on both sides of the sacrificial material.

### Claim 33 (depends on 30)

The method of claim 30 wherein the sacrificial material is conductive.

### Claim 34 (depends on 30)

The method of claim 30 wherein said removing is of all of the sacrificial material that is laterally between the insulator.