# US 10,770,464 B2 · Semiconductor device including bit line structure of dynamic random access memory (DRAM) and method for fabricating the same

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- Number: US 10,770,464 B2
- Document ID: US10770464B2
- Status: Granted
- Kind: B2
- Application number: 15/896,091
- Filed: 2018-02-14
- Published: 2019-07-18
- Granted: 2020-09-08
- Earliest claimed: 2018-01-18
- Assignees: United Microelectronics Corp.; Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicants: United Microelectronics Corp.; Fujian Jinhua Integrated Circuit Co., Ltd.
- Inventors: Chih-Chien Liu; Chia-Lung Chang; Tzu-Chin Wu; Wei-Lun Hsu
- Web page: https://patentgrep.com/patent/US10770464B2

## CPC

- H10B 12/482: {Bit lines}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/485: {Bit line contacts}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.

## Claims

### Claim 1

A semiconductor device, comprising:
a bit line structure on a substrate;
a first spacer around the bit line structure, wherein a bottom surface of the first spacer is even with a bottom surface of the bit line structure;
a second spacer on a sidewall of the first spacer, wherein the second spacer comprises a bottom portion and a top portion, the bottom portion and the top portion comprise different dielectric materials, the bottom portion comprises silicon oxide and the top portion comprises silicon nitride, sidewalls of the bottom portion are vertically aligned with sidewalls of the top portion, and the bottom surface of the first spacer is lower than a bottom surface of the second spacer; and
a third spacer on a sidewall of the second spacer, wherein the third spacer is asymmetrical shaped on two sides, with one side being L-shaped, while another side being I-shaped, and the first spacer extends downwardly into and contacting a shallow trench isolation disposed under the third spacer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first spacer and the third spacer comprise same material.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the bit line structure comprises a conductive layer, a metal layer on the conductive layer, and a mask layer on the metal layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein a top surface of the bottom portion is higher than a top surface of the metal layer.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein a bottom surface of the bottom portion is lower than a top surface of the conductive layer.

### Claim 6 (depends on 3)

The semiconductor device of claim 3, wherein a bottom surface of the top portion is higher than a top surface of the metal layer.