# US 10,770,463 B2 · Semiconductor devices including structures for reduced leakage current and method of fabricating the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,770,463 B2
- Document ID: US10770463B2
- Status: Granted
- Kind: B2
- Application number: 16/437,784
- Filed: 2019-06-11
- Published: 2019-09-26
- Granted: 2020-09-08
- Earliest claimed: 2017-04-12
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Min Hee Cho; Jun Soo Kim; Hui Jung Kim; Tae Yoon An; Satoru Yamada; Won Sok Lee; Nam Ho Jeon; Moon Young Jeong; Ki Jae Hur; Jae Ho Hong
- Web page: https://patentgrep.com/patent/US10770463B2

## CPC

- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- H10B 12/01: {Manufacture or treatment}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/46: comprising air gaps
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.

## Claims

### Claim 1

A method of fabricating a semiconductor device, the method comprising:
providing a substrate comprising a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer;
forming a source/drain region in a part of the upper semiconductor layer;
forming a first trench in the upper semiconductor layer, on one side of the source/drain region;
forming a first conductive pattern filling a part of the first trench;
forming a second trench in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer, on the other side of the source/drain region;
forming a second conductive pattern filling at least a part of the second trench; and
forming a unit active region and an element isolation region defining the unit active region, in the substrate,
wherein the first trench is formed in the unit active region of the substrate, and
wherein the second trench is formed in the element isolation region in the substrate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the element isolation region is not formed in the second trench, after forming the second trench.

### Claim 3

A method of fabricating a semiconductor device, the method comprising:
providing a substrate comprising a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer;
forming a source/drain region in a part of the upper semiconductor layer;
forming a first trench in the upper semiconductor layer, on one side of the source/drain region,
forming a first conductive pattern filling a part of the first trench;
forming a second trench in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer, on the other side of the source/drain region; and
forming a second conductive pattern filling at least a part of the second trench,
wherein the first trench has a lowest surface above the buried insulating layer.

### Claim 4

A method of fabricating a semiconductor device, the method comprising:
providing a substrate comprising a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer;
forming a first trench in the upper semiconductor layer, the first trench having a lowest surface above the buried insulating layer;
forming a first conductive pattern recessed in the first trench;
forming a second trench in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer;
forming a second conductive pattern in the second trench; and
forming a first source/drain region in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.

### Claim 5 (depends on 4)

The method of claim 4, further comprising forming a gate insulating layer on a sidewall and a bottom surface of the second trench,
wherein the second conductive pattern is on the gate insulating layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein an upper surface of the second conductive pattern is lower than an uppermost surface of the first conductive pattern.

### Claim 7 (depends on 6)

The method of claim 6, wherein an uppermost surface of the second conductive pattern is lower than an upper surface of the buried insulating layer.

### Claim 8 (depends on 5)

The method of claim 5, further comprising forming a capacitor on the substrate, wherein the first source/drain region is electrically connected to the capacitor.

### Claim 9 (depends on 5)

The method of claim 5, further comprising:
forming a third trench in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer;
forming a third conductive pattern in the third trench; and
forming a second source/drain region in the upper semiconductor layer between the first conductive pattern and the third conductive pattern,
wherein the first conductive pattern is interposed between the first source/drain region and the second source/drain region.

### Claim 10 (depends on 5)

The method of claim 5, further comprising forming a third conductive pattern on the second conductive pattern,
wherein the second conductive pattern has a work function that is higher than a work function of the third conductive pattern.

### Claim 11 (depends on 5)

The method of claim 5, further comprising forming a capping layer on the second conductive pattern, wherein the capping layer includes an air gap.

### Claim 12 (depends on 4)

The method of claim 4, wherein the second conductive pattern is electrically connected to the first source/drain region.

### Claim 13 (depends on 12)

The method of claim 12, wherein an upper surface of the second conductive pattern is higher than or equal to an upper surface of the upper semiconductor layer, and
wherein a lower surface of the second conductive pattern is lower than or equal to an upper surface of the lower semiconductor layer.