# US 10,770,462 B2 · Circuit and layout for single gate type precharge circuit for data lines in memory device

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- Number: US 10,770,462 B2
- Document ID: US10770462B2
- Status: Granted
- Kind: B2
- Application number: 16/197,185
- Filed: 2018-11-20
- Published: 2019-03-21
- Granted: 2020-09-08
- Earliest claimed: 2016-10-14
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Shinichi Miyatake
- Web page: https://patentgrep.com/patent/US10770462B2

## CPC

- H10B 12/00: Dynamic random access memory [DRAM] devices
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 7/08: Control thereof
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4094: Bit-line management or control circuits
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- H10B 20/60: {Peripheral circuit regions}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region; a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region; a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region; and a gate located over the first, second, and third channel regions. The first and second diffusion regions are located on a first side of the gate. The third and fourth diffusion regions are located on a second side of the gate opposite from the first side.

## Claims

### Claim 1

An apparatus comprising:
a first gate including first, second and third portions, the first, second and third portions located over first, second and third channel regions, respectively;
second and third gates disposed such that the first gate is arranged between the second and third gates, the second and third gates located over fourth and fifth channel regions, respectively;
first and second diffusion regions formed to define the fourth channel region; and
third and fourth diffusion regions formed to define the fifth channel region, wherein each of the first, second, third and fourth diffusion regions includes a respective elongated portion to define the first channel region between the elongated portion of the first diffusion region and the elongated portion of the third diffusion region, the second channel region between the elongated portion of the second diffusion region and the elongated portion of the third diffusion region, and the third channel region between the elongated portion of the second diffusion region and the elongated portion of the fourth diffusion region.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising:
fourth and fifth gates disposed such that the first gate is arranged between the fourth and fifth gates, the fourth and fifth gates located over sixth and seventh channel regions, respectively;
a fifth diffusion region formed to define the sixth channel region with the first diffusion region; and
a sixth diffusion region formed to define the seventh channel region with the fourth diffusion region.

### Claim 3 (depends on 1)

The apparatus of claim 1, further comprising a fifth diffusion region and a fourth gate disposed over a portion of the fifth diffusion region and a portion of the first diffusion region.

### Claim 4 (depends on 3)

The apparatus of claim 3, further comprising a sixth diffusion region and a fifth gate disposed over a portion of the sixth diffusion region and a portion of the fourth diffusion region.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the first gate is arranged between the fourth and fifth gates.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the first diffusion region and the fourth diffusion region are electrically coupled to each other, the second diffusion region and the third gate are electrically coupled to each other, and the third diffusion region and the second gate are electrically coupled to each other.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the second portion of the first gate is narrower than each of the first portion and the third portion of the first gate.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein each of the second and third gates includes a length extending in a direction perpendicularly to a direction of a length of the first gate.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the second gate is located on a first side of the first gate, and the third gate is located on a second side opposite from the first side of the first gate.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the first gate extends generally linearly between the first and second diffusion regions on a first side of the first gate and between the third and fourth diffusion regions on a second side of the first gate.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein each of the first, second, third, and fourth diffusion regions includes a material of a first conductivity type, and each of the first, second, and third channel regions includes a material of a second conductivity type.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the apparatus comprises a memory device, the memory device comprising:
a first memory cell array located at a first location of the memory device; and
a second memory cell array located at a second location of the memory device, wherein the first, second, third, and fourth diffusions are located at a third location of the memory device between the first and second locations.

### Claim 13 (depends on 1)

The apparatus of claim 1, wherein the apparatus comprises a memory device, and the first, second, third, and fourth diffusion regions are part of sensing circuitry of the memory device.

### Claim 14 (depends on 1)

The apparatus of claim 1, further comprising:
a first conductive contact coupled to the second diffusion region;
a first data line coupled to the second conductive contact;
a second conductive contact coupled to the third diffusion region; and
a second data line coupled to the third conductive contact.

### Claim 15 (depends on 1)

The apparatus of claim 1, further comprising:
a first conductive contact coupled to the first diffusion region; and
a second conductive contact coupled to the fourth diffusion region, wherein the conductive line is electrically coupled to the first and fourth diffusion regions through the first and second conductive contacts, respectively.

### Claim 16 (depends on 1)

The apparatus of claim 1, wherein the apparatus comprises a memory device, the memory device comprising a memory cell array and access lines located at a first location of the memory device, wherein the conductive line is located at a second location of the memory device, and each of the access lines and the conductive line has a length extending in a same direction.

### Claim 17

An apparatus comprising:
a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region;
a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region, wherein the first channel region, the portion of the first diffusion region, and the portion of the third diffusion region form part of a first transistor;
a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region, wherein the second channel region, the portion of the third diffusion region, and the portion of the second diffusion region form part of a second transistor;
a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region, wherein the third channel region, the portion of the second diffusion region, and the portion of the fourth diffusion region form part of a third transistor; and
a first gate located over the first, second, and third channel regions;
a second gate disposed over a portion of the first diffusion region and a portion of the second diffusion region; and
a third gate disposed over a portion of the third diffusion region and a portion of the fourth diffusion region.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein:
the first and fourth diffusion regions are electrically coupled to each other;
the second diffusion region and the third gate are electrically coupled to each other; and
the third diffusion region and the second gate are electrically coupled to each other.

### Claim 19 (depends on 17)

The apparatus of claim 17, wherein the first gate includes a first portion, a second portion, and a third portion, the second portion is between first and third portions, and the second portion is narrower than each of the first and third portions.

### Claim 20

An apparatus comprising:
a first diffusion region including a first elongated portion, a second diffusion region including a second elongated portion, a third diffusion region including a third elongated portion, and a fourth diffusion region including a fourth elongated portion;
a first channel region located between the first and third elongated portions, wherein the first channel region and the first and third elongated portions form part of a first transistor;
a second channel region located between second and third elongated portions, wherein the second channel region and the second and third elongated portions form part of a second transistor;
a third channel region located between the second and fourth elongated portions, wherein the third channel region and the second and fourth elongated portions form part of a third transistor;
a gate located over the first, second, and third channel regions, wherein the gate is shared by the first, second, and third transistors; and
a conductive line electrically coupled to the first and fourth diffusion regions.