# US 10,770,461 B2 · Enhanced field resistive RAM integrated with nanosheet technology

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,770,461 B2
- Document ID: US10770461B2
- Status: Granted
- Kind: B2
- Application number: 16/675,935
- Filed: 2019-11-06
- Published: 2020-03-05
- Granted: 2020-09-08
- Earliest claimed: 2018-04-23
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Pouya Hashemi; Takashi Ando; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US10770461B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 84/853: {comprising FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10N 70/253: {having three or more electrodes, e.g. transistor-like devices}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A semiconductor structure containing a resistive random access memory device integrated with a gate-all-around nanosheet CMOS device is provided. In one embodiment, the semiconductor structure includes a gate-all-around nanosheet CMOS device includes a functional gate structure present on, and between, each semiconductor channel material nanosheet of a nanosheet stack of suspended semiconductor channel material nanosheets. The structure of the present application further includes a resistive memory device located laterally adjacent to the gate-all-around nanosheet CMOS device that includes a second functional gate structure present on, and between, each recessed semiconductor channel material layer portion of a material stack, wherein a recessed sacrificial semiconductor material layer portion is located above and below each recessed semiconductor channel material layer portion. A shared source/drain region is located between the gate-all-around nanosheet CMOS device and the resistive memory device.

## Claims

### Claim 1

A method of forming a semiconductor structure, the method comprising:
providing a fin structure comprising a vertical stack of alternating layers of a sacrificial semiconductor material layer and a semiconductor channel material layer located on a surface of a semiconductor substrate, and a first sacrificial gate structure and a second sacrificial gate structure located on different portions of the fin structure.
forming a first mask partially covering the second sacrificial gate structure;
etching physically exposed portions of the fin structure to provide a nanosheet stack comprised of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet beneath the first sacrificial gate structure, and a material stack of alternating layers of a sacrificial semiconductor material layer portion and a semiconductor channel material layer portion beneath the second sacrificial gate structure and the first mask;
recessing each sacrificial semiconductor material nanosheet of the nanosheet stack and each sacrificial semiconductor material layer portion of the material stack;
forming an inner spacer within a gap formed by the recessing;
forming a second mask protecting the first sacrificial gate structure, the nanosheet stack, the inner spacers formed within the gap formed by recessing the sacrificial semiconductor material nanosheets of the nanosheet stack;
recessing the semiconductor channel material layer portions of the material stack;
removing the second mask;
forming a source/drain (S/D) region on physically exposed sidewalls of each semiconductor channel material nanosheet of the nanosheet stack and a S/D region on a physically exposed sidewall of each recessed semiconductor channel material layer portion of the material stack;
removing the first mask;
removing the first and second sacrificial gate structures, each recessed sacrificial semiconductor material nanosheet and a portion of each recessed sacrificial semiconductor material layer portion; and
forming a first functional gate structure wrapping around each suspended semiconductor channel material nanosheet, and a second functional gate structure on exposed surfaces of each recessed semiconductor channel material layer portion of the material stack.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming, after the removing of the second mask, an interlayer dielectric (IlD) material surrounding the first and second sacrificial gate structures.

### Claim 3 (depends on 2)

The method of claim 2, further comprising forming, after the forming of the first and second functional gate structures, an additional ILD material onto the ILD material and the first and second functional gate structures.

### Claim 4 (depends on 3)

The method of claim 3, further comprising forming, in any order, a source/drain contact structure directly contacting each S/D region, a first gate contact structure directly contacting the first gate structure, a second gate contact structure directly contacting the second gate structure, and a dummy gate contact structure directly contacting a topmost recessed semiconductor channel material layer portion of the material stack.

### Claim 5 (depends on 1)

The method of claim 1, wherein the forming of the S/D regions comprises an epitaxial growth process.

### Claim 6 (depends on 1)

The method of claim 1, further comprising performing a diffusion anneal to out-diffuse dopant from the S/D regions and into a portion of each of the semiconductor channel material nanosheets and each of the recessed semiconductor channel material layer portions.

### Claim 7 (depends on 1)

The method of claim 1, wherein each of the recessed semiconductor channel material layer portions has a width that is greater than a width of each of the sacrificial semiconductor material layer portions.

### Claim 8 (depends on 1)

The method of claim 1, wherein the second functional gate structure located on the exposed surfaces of each of the recessed semiconductor channel material layer portions of the material stack constituents a resistive memory device.

### Claim 9 (depends on 8)

The method of claim 8, wherein the recessed semiconductor channel material layer portions have sharp corners that facilitate electroforming of a filament of the resistive memory device.

### Claim 10 (depends on 1)

The method of claim 1, wherein each sacrificial semiconductor material is composed of a silicon germanium alloy, and each semiconductor channel material layer is composed of silicon or a III-V compound semiconductor.

### Claim 11 (depends on 1)

The method of claim 1, wherein the providing of the fin structure comprises:
epitaxially growing a semiconductor material stack of the alternating layers of the semiconductor material layer and the semiconductor channel material layer; and
patterning the semiconductor material stack.

### Claim 12 (depends on 1)

The method of claim 1, further comprising forming a gate spacer on a sidewall of the first and second sacrificial gate structures, wherein the gate spacer straddles over the fin structure.

### Claim 13 (depends on 1)

The method of claim 1, wherein the recessing of each sacrificial semiconductor material sheet of the nanosheet stack and each sacrificial semiconductor layer portion of the material stack comprises a lateral etch.

### Claim 14 (depends on 13)

The method of claim 13, wherein the lateral etch occurs inward from both sidewalls of each sacrificial semiconductor material sheet of the nanosheet stack, and wherein the lateral etch only occurs from a sidewall of each sacrificial semiconductor material layer portion that faces the first sacrificial gate structure.

### Claim 15 (depends on 1)

The method of claim 1, wherein the recessing of semiconductor channel material layers portions of the material stack forms a gap located above and below each recessed sacrificial semiconductor material layer portion, wherein the gap is located only on one side of the material stack that faces the first sacrificial gate structure.

### Claim 16 (depends on 1)

The method of claim 1, wherein the S/D region that is formed on the sidewall of each of the semiconductor channel material layer portions of the material stack is located on a side of the material stack facing the first sacrificial gate structure.

### Claim 17 (depends on 4)

The method of claim 4, wherein each source/drain contact structure, each gate contact structure and the dummy contact structure have a topmost surface that is coplanar with each other.

### Claim 18

A method of forming a semiconductor structure, the method comprising:
providing a fin structure comprising a vertical stack of alternating layers of a sacrificial semiconductor material layer and a semiconductor channel material layer located on a surface of a semiconductor substrate, and a first sacrificial gate structure and a second sacrificial gate structure located on different portions of the fin structure.
forming a first mask partially covering the second sacrificial gate structure;
etching physically exposed portions of the fin structure to provide a nanosheet stack comprised of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet beneath the first sacrificial gate structure, and a material stack of alternating layers of a sacrificial semiconductor material layer portion and a semiconductor channel material layer portion beneath the second sacrificial gate structure and the first mask;
recessing each sacrificial semiconductor material nanosheet of the nanosheet stack and each sacrificial semiconductor material layer portion of the material stack;
forming an inner spacer within a gap formed by the recessing;
forming a second mask protecting the first sacrificial gate structure, the nanosheet stack, the inner spacers formed within the gap formed by recessing the sacrificial semiconductor material nanosheets of the nanosheet stack;
recessing the semiconductor channel material layer portions of the material stack, wherein the recessed semiconductor channel material layer portions have sharp corners that facilitate electroforming of a filament of a resistive memory device;
removing the second mask;
forming a source/drain (S/D) region on physically exposed sidewalls of each semiconductor channel material nanosheet of the nanosheet stack and a S/D region on a physically exposed sidewall of each recessed semiconductor channel material layer portion of the material stack;
removing the first mask;
removing the first and second sacrificial gate structures, each recessed sacrificial semiconductor material nanosheet and a portion of each recessed sacrificial semiconductor material layer portion; and
forming a first functional gate structure wrapping around each suspended semiconductor channel material nanosheet, and a second functional gate structure on exposed surfaces of each recessed semiconductor channel material layer portion of the material stack.

### Claim 19 (depends on 18)

The method of claim 18, further comprising forming, in any order, a source/drain contact structure directly contacting each S/D region, a first gate contact structure directly contacting the first gate structure, a second gate contact structure directly contacting the second gate structure, and a dummy gate contact structure directly contacting a topmost recessed semiconductor channel material layer portion of the material stack.

### Claim 20 (depends on 19)

The method of claim 19, wherein each of the source/drain contact structure, the first gate contact structure, the second gate contact structure and the dummy gate contact structure are embedded in an interlayer dielectric material, and have a topmost surface that is coplanar with each other and coplanar with a topmost surface of the interlayer dielectric material.