# US 10,770,460 B2 · Vertical field-effect transistors for monolithic three-dimensional semiconductor integrated circuit devices

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- Number: US 10,770,460 B2
- Document ID: US10770460B2
- Status: Granted
- Kind: B2
- Application number: 16/741,973
- Filed: 2020-01-14
- Published: 2020-05-14
- Granted: 2020-09-08
- Earliest claimed: 2018-10-16
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Joshua M. Rubin
- Web page: https://patentgrep.com/patent/US10770460B2

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 88/01: {Manufacture or treatment}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Devices and methods are provided for fabricating vertical field-effect transistor devices for monolithic three-dimensional semiconductor integrated circuit devices. A semiconductor structure is formed to include a substrate and a stack of layers formed on the substrate including a first active semiconductor layer, an insulating layer, and a second active semiconductor layer. A vertical fin structure is formed by patterning the first and second active semiconductor layers and the insulating layer, wherein the vertical fin structure includes first and second vertical semiconductor fins, and an insulating fin spacer disposed between the first and second vertical semiconductor fins. The first and second vertical semiconductor fins are utilized to fabricate first and second vertical field-effect transistor devices on first and second device layers of a monolithic three-dimensional semiconductor integrated circuit device.

## Claims

### Claim 1

A method, comprising:
forming a vertical fin structure on a first substrate, wherein the vertical fin structure comprises a first vertical semiconductor fin, a fin insulating spacer disposed on the first vertical semiconductor fin, and a second vertical semiconductor fin disposed on the fin insulating spacer;
forming a sacrificial layer of insulating material on the first substrate, wherein the sacrificial layer of insulating material encapsulates the first vertical semiconductor fin of the vertical fin structure; and
forming a first device layer on the sacrificial layer of insulating material, wherein the first device layer comprises a first vertical field-effect transistor device which comprises the second vertical semiconductor fin of the vertical fin structure.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
bonding a second substrate to the first device layer;
removing the first substrate to expose the sacrificial layer of insulating material;
removing the sacrificial layer of insulating material to expose the first vertical semiconductor fin; and
forming a second device layer over first device layer, wherein the second device layer comprises a second vertical field-effect transistor device which comprises the first vertical semiconductor fin.

### Claim 3 (depends on 2)

The method of claim 2, further comprising forming a capping layer on the sacrificial layer of insulating material prior to forming the first device layer, wherein the capping layer is formed of a material that has etch selectivity with respect to the sacrificial layer of insulating material.

### Claim 4 (depends on 3)

The method of claim 3, wherein the capping layer is formed of silicon nitride and wherein the sacrificial layer of insulating material is formed of silicon oxide.

### Claim 5 (depends on 3)

The method of claim 3, wherein the capping layer is disposed substantially coplanar with the fin insulating spacer disposed between the first and second vertical semiconductor fins.

### Claim 6 (depends on 3)

The method of claim 3, wherein removing the sacrificial layer of insulating material to expose the first vertical semiconductor fin comprises performing an etch process to etch the sacrificial layer of insulating material down to the capping layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the vertical fin structure on the first substrate comprises:
forming a first semiconductor layer on the first substrate;
forming an insulating layer on the first semiconductor layer;
forming a second semiconductor layer on the insulating layer; and
patterning the first semiconductor layer, the insulating layer, and the second semiconductor layer down to the first substrate to thereby form the vertical fin structure.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first and second vertical semiconductor fins are formed of epitaxial semiconductor material.

### Claim 9 (depends on 8)

The method of claim 8, wherein the epitaxial semiconductor material comprises epitaxial silicon.

### Claim 10 (depends on 8)

The method of claim 8, wherein the epitaxial semiconductor material comprises an epitaxial silicon-germanium alloy.

### Claim 11 (depends on 7)

The method of claim 7, wherein the epitaxial semiconductor material comprises a III-V compound semiconductor material.

### Claim 12 (depends on 2)

The method of claim 2, wherein:
the first vertical field-effect transistor device comprises:
a first source/drain region disposed at first end of the second vertical semiconductor fin and a second source/drain region disposed at second end of the second vertical semiconductor fin;
a first source/drain contact disposed surrounding the first source/drain region;
a first metallic gate structure disposed surrounding the second vertical semiconductor fin; and
a first insulating spacer layer disposed between the first metallic gate structure and the first source/drain contact; and
the second vertical field-effect transistor device comprises:
a third source/drain region disposed at first end of the first vertical semiconductor fin and a fourth source/drain region disposed at second end of the first vertical semiconductor fin;
a second source/drain contact disposed surrounding the third source/drain region;
a second metallic gate structure disposed surrounding the first vertical semiconductor fin; and
a second insulating spacer layer disposed between the second metallic gate structure and the second source/drain contact.

### Claim 13 (depends on 12)

The method of claim 12, wherein the first and third source/drain regions comprise doped first ends of the first and second vertical semiconductor fins adjacent to the fin insulating spacer.

### Claim 14 (depends on 12)

The method of claim 12, wherein forming the first and second device layers comprises:
forming a third gate insulating spacer on the first metallic gate structure; and
forming a fourth gate insulating spacer on the second metallic gate structure.

### Claim 15

A method, comprising:
forming an etch stop layer on a first substrate;
forming a first semiconductor layer on the etch stop layer;
forming an insulating layer on the first semiconductor layer;
forming a second semiconductor layer on the insulating layer;
patterning the first semiconductor layer, the insulating layer, and the second semiconductor layer down to the etch stop layer to thereby form a vertical fin structure comprising a first vertical semiconductor fin, a second vertical semiconductor fin, and a fin insulating spacer disposed between the first and second vertical semiconductor fins;
forming a sacrificial layer of insulating material on the etch stop layer over the first substrate, wherein the sacrificial layer of insulating material encapsulates the first vertical semiconductor fin of the vertical fin structure;
forming a capping layer on the sacrificial layer of insulating material; and
forming a first device layer on the capping layer, wherein the first device layer comprises a first vertical field-effect transistor device which comprises the second vertical semiconductor fin of the vertical fin structure.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
bonding a second substrate to the first device layer;
removing the first substrate and the etch stop layer to expose the sacrificial layer of insulating material;
removing the sacrificial layer of insulating material to expose the first vertical semiconductor fin; and
forming a second device layer over first device layer, wherein the second device layer comprises a second vertical field-effect transistor device which comprises the first vertical semiconductor fin of the vertical fin structure.

### Claim 17 (depends on 15)

The method of claim 15, wherein the capping layer is formed of a material that has etch selectivity with respect to the sacrificial layer of insulating material.

### Claim 18 (depends on 17)

The method of claim 17, wherein the capping layer is formed of silicon nitride and wherein the sacrificial layer of insulating material is formed of silicon oxide.

### Claim 19 (depends on 15)

The method of claim 15, wherein the capping layer is disposed substantially coplanar with the fin insulating spacer disposed between the first and second vertical semiconductor fins of the vertical fin structure.

### Claim 20 (depends on 16)

The method of claim 16, wherein removing the sacrificial layer of insulating material to expose the first vertical semiconductor fin comprises performing an etch process to etch the sacrificial layer of insulating material down to the capping layer.