# US 10,770,459 B2 · CMOS devices containing asymmetric contact via structures

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- Number: US 10,770,459 B2
- Document ID: US10770459B2
- Status: Granted
- Kind: B2
- Application number: 16/227,565
- Filed: 2018-12-20
- Published: 2019-09-26
- Granted: 2020-09-08
- Earliest claimed: 2018-03-23
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Dai Iwata; Yasushi Ishii; Hiroshi Nakatsuji; Kiyokazu Shishido; Hiroyuki Ogawa
- Web page: https://patentgrep.com/patent/US10770459B2

## CPC

- H10D 64/0113: {the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/514: {characterised by the insulating layers}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/076: {in via holes or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10W 20/036: {the barrier, adhesion or liner layers being within a main fill metal}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A silicon oxide liner, a silicon nitride liner, and a planarization silicon oxide layer may be sequentially formed over p-type and n-type field effect transistors. A patterned dielectric material layer covers an entirety of the n-type field effect transistor and does not cover at least a fraction of each area of p-doped active regions. An anisotropic etch process is performed to form p-type active region via cavities extending to a respective top surface of the p-doped active regions and n-type active region via cavities having a respective bottom surface at, or within, one of the silicon nitride liner and the silicon oxide liner. Boron-doped epitaxial pillar structures may be formed on top surfaces of the p-type active regions employing a selective epitaxy process. The n-type active region via cavities are extended to top surfaces of the n-doped active regions. Contact via structures are formed in the via cavities.

## Claims

### Claim 1

A CMOS device, comprising:
a p-type field effect transistor containing p-doped active regions and located on a semiconductor substrate;
an n-type field effect transistor containing n-doped active regions and located on the semiconductor substrate;
boron-doped epitaxial pillar structures contacting a top surface of, and epitaxially aligned to, a respective one of the p-doped active regions;
first active region contact via structures contacting a top surface of a respective one of the boron-doped epitaxial pillar structures;
second active region contact via structures contacting a top surface of a respective one of the n-doped active regions; and
a silicon oxide material portion laterally surrounding one of the second active region contact via structures and not overlying the p-type field effect transistor.

### Claim 2 (depends on 1)

The CMOS device of claim 1, wherein the silicon oxide material portion is vertically spaced from top surfaces of the n-doped active regions and is located below a horizontal plane including top surfaces of the first active region contact via structures and the second active region contact via structures.

### Claim 3 (depends on 1)

The CMOS device of claim 1, wherein the silicon oxide material portion comprises a first tubular silicon oxide spacer that contacts, and laterally surrounds, the one of the second active region contact via structures.

### Claim 4 (depends on 3)

The CMOS device of claim 3, further comprising a second tubular silicon oxide spacer that contacts a top surface of one of the boron-doped epitaxial pillar structures.

### Claim 5 (depends on 4)

The CMOS device of claim 4, further comprising a planarization silicon oxide layer that continuously extends over that p-type field effect transistor and the n-type field effect transistor and laterally surrounds each of the first tubular silicon oxide spacer and the second silicon oxide spacer.

### Claim 6 (depends on 5)

The CMOS device of claim 5, wherein an annular top surface of the first tubular silicon oxide spacer is located at a greater vertical distance from a horizontal plane including a topmost surface of the semiconductor substrate than an annular top surface of the second tubular silicon oxide spacer is from the horizontal plane including the topmost surface of the semiconductor substrate.

### Claim 7 (depends on 5)

The CMOS device of claim 5, further comprising:
a silicon oxide liner contacting top surfaces of the p-doped active regions and the n-doped active regions; and
a silicon nitride liner overlying the first silicon oxide liner and extending over the p-type field effect transistor and the n-type field effect transistor,
wherein the first tubular silicon oxide spacer contacts an annular portion of a top surface of silicon nitride liner.

### Claim 8 (depends on 7)

The CMOS device of claim 7, wherein:
each the boron-doped epitaxial pillar structures contacts sidewalls of a respective opening through the silicon oxide liner and the silicon nitride liner; and
the second tubular silicon oxide spacer is spaced from, and is located above, a top surface of the silicon nitride liner.

### Claim 9 (depends on 4)

The CMOS device of claim 4, wherein the first tubular silicon oxide spacer and the second tubular silicon oxide spacer have a same lateral thickness and a same material composition.

### Claim 10 (depends on 4)

The CMOS device of claim 4, wherein:
the boron-doped epitaxial pillar structures protrude through the silicon oxide liner and the silicon nitride liner;
the first active region contact via structures extend through the planarization silicon oxide layer to contact the top surface of the respective one of the boron-doped epitaxial pillar structures; and
the second active region contact via structures extend through the planarization silicon oxide layer, the silicon nitride liner, and the silicon oxide liner to contact the top surface of the respective one of the n-doped active regions.

### Claim 11 (depends on 1)

The CMOS device of claim 1, wherein each of the first active region contact via structures and the second active region contact via structures comprises:
a respective metallic barrier liner having a same first material composition and a same thickness; and
a respective metal fill material portion having a same second metal composition.

### Claim 12 (depends on 1)

The CMOS device of claim 1, wherein:
the p-doped active regions include boron atoms at a first average atomic concentration;
the boron-doped epitaxial pillar structures include boron atoms at a second average atomic concentration that is different from the first average atomic concentration; and
top surfaces of the p-doped active regions and top surfaces of the n-doped active regions are within a horizontal plane that includes bottom surfaces of gate dielectrics of the p-type field effect transistor and the n-type field effect transistor.

### Claim 13 (depends on 1)

A three-dimensional NAND memory device, comprising:
the CMOS device of claim 1 located over a substrate;
an alternating stack of insulating layers and word lines located over the CMOS device; and
memory stack structures extending through the alternating stack and comprising a respective memory film and a vertical semiconductor channel.