# US 10,770,453 B2 · Semiconductor device having an emitter region and a contact region inside a mesa portion

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- Number: US 10,770,453 B2
- Document ID: US10770453B2
- Status: Granted
- Kind: B2
- Application number: 15/885,832
- Filed: 2018-02-01
- Published: 2018-06-07
- Granted: 2020-09-08
- Earliest claimed: 2016-02-15
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Yuichi Onozawa; Kota Ohi
- Web page: https://patentgrep.com/patent/US10770453B2

## CPC

- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/212: {Through-implantation}
- H10P 30/22: using masks
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D 8/422: {PN diodes having the PN junctions in mesas}
- H10D 10/441: {having an emitter-base junction ending at a main surface of the body and a base-collector junction ending at a lateral surface of the body}
- H10D 12/035: {Etching a recess in the emitter region (having a recessed gate H10D12/038)}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/133: {Emitter regions of BJTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device is provided that has a semiconductor substrate, a drift layer of a first conductivity type formed in the semiconductor substrate, a base region of a second conductivity type formed in the semiconductor substrate and above the drift layer, and an accumulation region of the first conductivity type provided between the drift layer and the base region and having an impurity concentration higher than an impurity concentration in the drift layer, wherein the accumulation region has a first accumulation region and a second accumulation region that is formed more shallowly than the first accumulation region is and on a side of a boundary with a region that is different from the accumulation region in a planar view.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate;
a drift layer of a first conductivity type formed in the semiconductor substrate;
a base region of a second conductivity type formed in the semiconductor substrate and above the drift layer; and
an accumulation region of the first conductivity type provided between the drift layer and the base region and having an impurity concentration higher than an impurity concentration in the drift layer, wherein
the accumulation region has:
a plurality of first accumulation regions; and
a second accumulation region,
wherein the second accumulation region is in direct contact with at least one of the first accumulation regions on a side of the at least one first accumulation region such that the plurality of first accumulation regions are only on one side of the second accumulation region in a planar view,
the semiconductor device further comprising a transistor portion formed in the semiconductor substrate,
wherein the transistor portion has:
a plurality of trench portions that are formed in a front surface of the semiconductor substrate and are arrayed in a predetermined direction; and
in the front surface of the semiconductor substrate, an emitter region of the first conductivity type having an impurity concentration higher than the impurity concentration in the drift layer formed between the plurality of trench portions,
wherein each of the plurality of first accumulation regions and the second accumulation region are formed between the plurality of trench portions,
wherein, at one end of an array direction in the transistor portion, the transistor portion has a boundary region in which the emitter region is not formed between the plurality of trench portions, and
wherein the boundary region is formed in the transistor portion on a side of a boundary with a diode portion formed in the semiconductor substrate.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein a width of the second accumulation region in the boundary region is equal to a width of a mesa surrounded by the plurality of trench portions.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein, in the front surface of the semiconductor substrate in the boundary region, the semiconductor substrate has a contact region of the second conductivity type having an impurity concentration higher than an impurity concentration in the base region.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein, in the boundary region, the drift layer is connected to the base region.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the second accumulation region includes a region formed at a depth at least as deep as a central position of the base region in a depth direction.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein an impurity concentration at a lower end of the second accumulation region is lower than an impurity concentration at a lower end of each of the plurality of first accumulation regions.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, further comprising a well region of the second conductivity type in the front surface of the semiconductor substrate on an extending direction side to which the transistor portion extends in a planar view,
wherein the second accumulation region is on a side of the at least one first accumulation region with the well region in a planar view.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein, in an extending direction of the plurality of trench portions, the base region is provided between the second accumulation region and the well region.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the emitter region is not formed above each of the plurality of first accumulation regions and the second accumulation region.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein each of the plurality of first accumulation regions and the second accumulation region are connected to the drift layer.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein
the second accumulation region is formed more shallowly than each first accumulation region.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11, wherein, in an extending direction of the plurality of trench portions, a depth of the second accumulation region gradually becomes shallower as a distance from the at least one first accumulation region increases.

### Claim 13 (depends on 1)

The semiconductor device according to claim 1, wherein, the transistor portion has the boundary region at both of the one end of the array direction in the transistor portion and other end opposite to the one end.

### Claim 14

A semiconductor device comprising:
a semiconductor substrate;
a drift layer of a first conductivity type formed in the semiconductor substrate;
a base region of a second conductivity type formed in the semiconductor substrate and above the drift layer; and
an accumulation region of the first conductivity type provided between the drift layer and the base region and having an impurity concentration higher than an impurity concentration in the drift layer, wherein
the accumulation region has:
a plurality of first accumulation regions; and
a second accumulation region,
wherein the second accumulation region is in direct contact with at least one of the first accumulation regions on a side of the at least one first accumulation region such that the plurality of first accumulation regions are only on one side of the second accumulation region in a planar view,
the semiconductor device further comprising a transistor portion formed in the semiconductor substrate,
wherein the transistor portion has:
a plurality of trench portions that are formed in a front surface of the semiconductor substrate and are arrayed in a predetermined direction; and
in the front surface of the semiconductor substrate, an emitter region of the first conductivity type having an impurity concentration higher than the impurity concentration in the drift layer formed between the plurality of trench portions,
wherein each of the plurality of first accumulation regions and the second accumulation region are formed between the plurality of trench portions,
wherein, at one end of an array direction in the transistor portion, the transistor portion has a boundary region in which the emitter region is not formed between the plurality of trench portions, and
wherein a depth of the second accumulation region gradually varies in a direction parallel to the front surface of the semiconductor substrate.

### Claim 15

A semiconductor device comprising:
a semiconductor substrate;
a drift layer of a first conductivity type formed in the semiconductor substrate;
a base region of a second conductivity type formed in the semiconductor substrate and above the drift layer;
an accumulation region of the first conductivity type provided between the drift layer and the base region and having an impurity concentration higher than an impurity concentration in the drift layer; and
a plurality of trench portions that are formed in a front surface of the semiconductor substrate and are arrayed in a predetermined array direction,
wherein, at one end of the array direction of the plurality of trench portions, the accumulation region has:
a plurality of first accumulation regions; and
a second accumulation region,
wherein the second accumulation region is in direct contact with at least one of the first accumulation regions on a side of the at least one first accumulation region such that the plurality of first accumulation regions are only on one side of the second accumulation region in a planar view,
the semiconductor device further comprising a transistor portion formed in the semiconductor substrate,
wherein the transistor portion has, in the front surface of the semiconductor substrate, an emitter region of the first conductivity type having an impurity concentration higher than the impurity concentration in the drift layer formed between the plurality of trench portions,
wherein, at one end of an array direction in the transistor portion, the transistor portion has a boundary region in which the emitter region is not formed between the plurality of trench portions, and
wherein the boundary region is formed in the transistor portion on a side of a boundary with a diode portion formed in the semiconductor substrate.

### Claim 16 (depends on 15)

The semiconductor device according to claim 15, wherein
the second accumulation region is formed more shallowly than each first accumulation region.

### Claim 17

A semiconductor device comprising:
a semiconductor substrate;
a drift layer of a first conductivity type formed in the semiconductor substrate;
a base region of a second conductivity type formed in the semiconductor substrate and above the drift layer;
an accumulation region of the first conductivity type provided between the drift layer and the base region and having an impurity concentration higher than an impurity concentration in the drift layer; and
a plurality of trench portions that are formed in a front surface of the semiconductor substrate and are arrayed in a predetermined array direction,
wherein, at one end of the array direction of the plurality of trench portions, the accumulation region has:
a plurality of first accumulation regions; and
a second accumulation region,
wherein the second accumulation region is in direct contact with at least one of the first accumulation regions on a side of the at least one first accumulation region such that the plurality of first accumulation regions are only on one side of the second accumulation region in a planar view,
the semiconductor device further comprising a transistor portion formed in the semiconductor substrate,
wherein the transistor portion has, in the front surface of the semiconductor substrate, an emitter region of the first conductivity type having an impurity concentration higher than the impurity concentration in the drift layer formed between the plurality of trench portions,
wherein, at one end of an array direction in the transistor portion, the transistor portion has a boundary region in which the emitter region is not formed between the plurality of trench portions, and
wherein a depth of the second accumulation region gradually varies in a direction parallel to the front surface of the semiconductor substrate.