# US 10,770,452 B2 · Apparatus and methods for electrical overstress protection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,452 B2 - Document ID: US10770452B2 - Status: Granted - Kind: B2 - Application number: 15/393,590 - Filed: 2016-12-29 - Published: 2017-07-06 - Granted: 2020-09-08 - Earliest claimed: 2015-12-30 - Assignees: Skyworks Solutions, Inc. - Applicants: Skyworks Solutions, Inc. - Inventors: Leslie Paul Wallis - Web page: https://patentgrep.com/patent/US10770452B2 ## CPC - H10D 89/931: {characterised by the dispositions of the protective arrangements} - H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits} - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10D 89/611: {using diodes as protective elements} - H10D 89/811: {using FETs as protective elements} - H10D 89/911: {using passive elements as protective elements} - H10D 89/921: {characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses} - H10W 20/427: {Power or ground buses} - H10W 72/00: Interconnections or connectors in packages - H02H 3/14: responsive to occurrence of voltage on parts normally at earth potential {(monitoring earth connection H02H5/105)} - H02H 3/16: responsive to fault current to earth, frame or mass (with balanced or differential arrangement H02H3/26 {; monitoring earth connection H02H5/105}) - H10W 72/29: Bond pads specially adapted therefor - H10W 72/59: Bond pads specially adapted therefor - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H10W 80/743: {having disposition changed during the connecting} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Apparatus and methods for electrical overstress (EOS) protection circuits are provided herein. In certain configurations, an EOS protection circuit includes an overstress sensing circuit electrically connected between a pad and a first supply node, an impedance element electrically connected between the pad and a signal node, a controllable clamp electrically connected between the signal node and the first supply node and selectively activatable by the overstress sensing circuit, and an overshoot limiting circuit electrically connected between the signal node and a second supply node. The overstress sensing circuit activates the controllable clamp when an EOS event is detected at the pad. Thus, the EOS protection circuit is arranged to divert charge associated with the EOS event away from the signal node to provide EOS protection. ## Claims ### Claim 1 An integrated circuit with electrical overstress protection, the integrated circuit comprising: a pad; an internal circuit electrically connected to a signal node; and an overstress protection circuit including an impedance element having a first end electrically connected to the pad and a second end electrically connected to the signal node, an overstress sensing circuit electrically connected between the first end of the impedance element and a first supply node, a controllable clamp electrically connected between the second end of the impedance element and the first supply node, a first reverse protection circuit electrically connected between the first end of the impedance element and the first supply node, a second reverse protection circuit electrically connected between the second end of the impedance element and the first supply node, and an overshoot limiting circuit electrically connected between the signal node and a second supply node, the overstress sensing circuit configured to activate the controllable clamp to conduct a current from the second end of the impedance element to the first supply node in response to detecting an electrical overstress event at the first end of the impedance element. ### Claim 2 (depends on 1) The integrated circuit of claim 1 wherein the overstress sensing circuit includes a plurality of diodes and a first field-effect transistor configured to activate when the electrical overstress event generates a flow of current through the plurality of diodes. ### Claim 3 (depends on 2) The integrated circuit of claim 2 wherein the controllable clamp includes a second field-effect transistor electrically connected with the first field-effect transistor as a current mirror. ### Claim 4 (depends on 3) The integrated circuit of claim 3 wherein the controllable clamp further includes a clamp diode electrically connected in series with the second field-effect transistor between the signal node and the first supply node. ### Claim 5 (depends on 1) The integrated circuit of claim 1 wherein the first supply node is a ground rail and the second supply node is a power supply rail. ### Claim 6 (depends on 1) The integrated circuit of claim 1 wherein the overshoot limiting circuit includes at least one diode configured to control a trigger voltage of the overshoot limiting circuit. ### Claim 7 (depends on 6) The integrated circuit of claim 6 wherein the overshoot limiting circuit includes two or more diodes electrically connected in series between the signal node and the second supply node. ### Claim 8 (depends on 1) The integrated circuit of claim 1 wherein the impedance element includes a resistor. ### Claim 9 (depends on 1) The integrated circuit of claim 1 further including a supply clamp electrically connected between the second supply node and the first supply node. ### Claim 10 An overstress protection circuit for a semiconductor chip, the overstress protection circuit comprising: an impedance element having a first end electrically connected to a pad and a second end electrically connected to a signal node; a controllable clamp electrically connected between the second end of the impedance element and a first supply node; an overstress sensing circuit electrically connected between the first end of the impedance element and the first supply node, the overstress sensing circuit configured to activate the controllable clamp to conduct a current from the second end of the impedance element to the first supply node in response to detecting an electrical overstress event at the first end of the impedance element; an overshoot limiting circuit electrically connected between the signal node and a second supply node, the overstress protection circuit arranged so as to divert charge associated with the electrical overstress event away from the signal node to thereby provide overstress protection; and a first reverse protection circuit electrically connected between the first end of the impedance element and the first supply node, and a second reverse protection circuit electrically connected between the second end of the impedance element and the first supply node. ### Claim 11 (depends on 10) The overstress protection circuit of claim 10 wherein the overstress sensing circuit includes a plurality of diodes and a first field-effect transistor configured to activate when the electrical overstress event generates a flow of current through the plurality of diodes. ### Claim 12 (depends on 11) The overstress protection circuit of claim 11 wherein the controllable clamp includes a second field-effect transistor having a gate voltage that is controlled based on a gate voltage of the first field-effect transistor. ### Claim 13 (depends on 12) The overstress protection circuit of claim 12 wherein the controllable clamp further includes a clamp diode electrically connected in series with the second field-effect transistor between the signal node and the first supply node. ### Claim 14 (depends on 12) The overstress protection circuit of claim 12 wherein the first and second field-effect transistors are electrically connected as a current mirror. ### Claim 15 (depends on 10) The overstress protection circuit of claim 10 wherein the first supply node is a ground rail and the second supply node is a power supply rail. ### Claim 16 (depends on 10) The overstress protection circuit of claim 10 wherein the overshoot limiting circuit includes at least one diode configured to control a trigger voltage of the overshoot limiting circuit. ### Claim 17 (depends on 10) The overstress protection circuit of claim 10 wherein the impedance element includes a resistor. ### Claim 18 A method of providing overstress protection, the method comprising: providing a voltage drop from a pad to a signal node in response to an electrical overstress event at the pad using an impedance element, the impedance element having a first end electrically connected to the pad and a second end electrically connected to the signal node; detecting the electrical overstress event at the first end of the impedance element using an overstress sensing circuit connected between the first end of the impedance element and a first supply node; activating a controllable clamp to conduct a current between the second end of the impedance element and the first supply node in response to detecting the electrical overstress event at the first end of the impedance element using the overstress sensing circuit; protecting the signal node from overshoot before the controllable clamp is activated using an overshoot limiting circuit; and protecting an internal circuit connected to the signal node using a first reverse protection circuit electrically connected between the first end of the impedance element and the first supply node, and a second reverse protection circuit electrically connected between the second end of the impedance element and the first supply node. ### Claim 19 The method of 18 wherein activating the controllable clamp includes mirroring a current flowing through the overstress sensing circuit. ### Claim 20 The method of 18 wherein protecting the signal node from overshoot includes forward biasing at least one diode.