# US 10,770,448 B2 · Methods of manufacturing semiconductor devices

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- Number: US 10,770,448 B2
- Document ID: US10770448B2
- Status: Granted
- Kind: B2
- Application number: 15/787,871
- Filed: 2017-10-19
- Published: 2018-03-01
- Granted: 2020-09-08
- Earliest claimed: 2015-01-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jhon Jhy Liaw
- Web page: https://patentgrep.com/patent/US10770448B2

## CPC

- H10D 89/10: Integrated device layouts
- H10B 10/12: {comprising a MOSFET load element}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/514: {characterised by the insulating layers}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10P 50/73: {using masks for insulating materials}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/853: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor device includes forming a first masking layer and second masking layer over a substrate. The first masking layer includes an opening over an active area and a spacer in the substrate, and the second masking layer blocks a portion of the opening in the first masking layer. The method includes performing an etching process, using the first masking layer and the second masking layer as an etching mask, to form a contact opening which exposes a portion of the active area and a portion of the spacer, and forming a contact plug in the contact opening and over the exposed portion of the active area and the exposed portion of the spacer.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming a first masking layer over a substrate, the first masking layer comprising an opening over an active area and a spacer in the substrate;
forming a second masking layer over the substrate, the second masking layer having a block blocking a portion of the opening in the first masking layer;
performing an etching process, using the first masking layer and the second masking layer as an etching mask, to form a contact opening which exposes a portion of the active area and a portion of the spacer, wherein the contact opening has a first edge and a second edge located at opposite sides of the contact opening, and wherein the first edge is defined by an edge of the opening in the first masking layer and the second edge is defined by an edge of the block in the second masking layer; and
forming a contact plug in the contact opening and over the exposed portion of the active area and the exposed portion of the spacer.

### Claim 2 (depends on 1)

The method of claim 1, wherein
the substrate comprises an additional feature,
the forming the contact opening exposes a portion of the additional feature,
the forming the contact plug comprises forming the contact plug over the exposed portion of the additional feature, and
the additional feature is one or more of a gate electrode, a hard mask over a gate electrode, another spacer, a source/drain region in the active area, or a silicide feature.

### Claim 3 (depends on 1)

The method of claim 1, wherein
the forming the first masking layer comprises performing a lithography process using a clear tone mask, and
the forming the second masking layer comprises performing a lithography process using a dark tone mask.

### Claim 4 (depends on 1)

The method of claim 1, wherein
the forming the first masking layer comprises using a first photoresist layer to define the opening in a hard mask layer,
the forming the second masking layer comprises forming a second photoresist layer on a dielectric layer in the opening, and
the performing the etching process comprises using the hard mask layer and the second photoresist layer as the etching mask.

### Claim 5 (depends on 1)

The method of claim 1, wherein
the forming the first masking layer comprises using a first photoresist layer to define the opening in an upper hard mask layer,
the forming the second masking layer comprises forming a second photoresist layer on a lower hard mask layer in the opening, and
the performing the etching process comprises using the upper hard mask layer and the lower hard mask layer as the etching mask.

### Claim 6 (depends on 1)

The method of claim 1, wherein the performing the etching process using the etching mask comprises forming another contact opening which exposes a portion of another active area, the contact opening and the another contact opening being separated by the second masking layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the portion of the active area includes a first dopant type, and the portion of the another active area includes a second dopant type different from the first dopant type.

### Claim 8 (depends on 6)

The method of claim 6, wherein the forming the contact plug in the contact opening comprises performing a planarizing operation that separates the contact plug from the another contact plug.

### Claim 9 (depends on 1)

The method of claim 1, wherein the forming the contact plug in the contact opening forms an electrical connection between the exposed portion of the active area and a gate electrode in the substrate.

### Claim 10

A method of manufacturing a FinFET structure, the method comprising:
forming a first masking layer over the FinFET structure, the first masking layer comprising an opening over a first fin of the FinFET structure and a first spacer of the FinFET structure;
forming a second masking layer over the FinFET structure, the second masking layer having a block blocking a portion of the opening in the first masking layer;
using the first masking layer and the second masking layer as an etching mask, etching a portion of a dielectric layer of the FinFET structure to form a contact opening, wherein the contact opening has a first edge and a second edge located at opposite sides of the contact opening, and wherein the first edge is defined by an edge of the opening in the first masking layer and the second edge is defined by an edge of the block in the second masking layer; and
forming a contact plug in the contact opening along the first spacer and overlying and contacting a portion of the first fin.

### Claim 11 (depends on 10)

The method of claim 10, wherein
the forming the first masking layer comprises using a first photoresist layer to define the opening in a first hard mask layer, and
the etching the portion of the dielectric layer comprises using the first hard mask layer as a part of the etching mask.

### Claim 12 (depends on 11)

The method of claim 11, wherein
the forming the second masking layer comprises forming a second photoresist layer on the dielectric layer in the opening, and
the etching the portion of the dielectric layer comprises using the second photoresist layer as another part of the etching mask.

### Claim 13 (depends on 11)

The method of claim 11, wherein
the forming the second masking layer comprises forming a second photoresist layer on a second hard mask layer in the opening, and
the etching the portion of the dielectric layer comprises using the second hard mask layer as another part of the etching mask.

### Claim 14 (depends on 11)

The method of claim 11, wherein using the first photoresist layer to define the opening in the first hard mask layer comprises using a positive photoresist patterned by a clear tone mask.

### Claim 15 (depends on 14)

The method of claim 14, wherein the forming the second masking layer comprises using another positive photoresist patterned by a dark tone mask.

### Claim 16 (depends on 10)

The method of claim 10, wherein the forming the second masking layer over the FinFET structure comprises forming the second masking layer between the first fin and a second fin of the FinFET structure.

### Claim 17 (depends on 10)

The method of claim 10, wherein the forming the contact plug in the contact opening comprises forming the contact plug along a second spacer of the FinFET structure.

### Claim 18

A method of manufacturing a memory cell, the method comprising:
forming a first masking layer over the memory cell, the first masking layer comprising a first opening over a first half-cell of the memory cell and a second opening over a second half-cell of the memory cell;
forming a second masking layer over the memory cell, the second masking layer having a block blocking a portion of the first opening and a portion of the second opening;
using the first masking layer and the second masking layer as an etching mask, performing an etching process to form a first contact opening in the first half-cell and a second contact opening in the second half-cell, wherein each of the first contact opening and the second contact opening has a first edge and a second edge located at opposite sides, wherein the first edge of the first contact opening is defined by an edge of the first opening in the first masking layer and the second edge of the first contact opening is defined by an edge of the block in the second masking layer at an edge an edge of the block in the second masking layer; and
forming a first contact plug in the first contact opening and a second contact plug in the second opening,
wherein
the forming each of the first contact opening and the second contact opening exposes a portion of a source/drain region of a transistor of the corresponding half-cell and a portion of a gate spacer of the corresponding half-cell, and
the forming each of the first contact plug and the second contact plug comprises forming the corresponding contact plug over the exposed portion of the corresponding source/drain region and the exposed portion of the corresponding gate spacer.

### Claim 19 (depends on 18)

The method of claim 18, wherein
the first opening is over a first well having a first dopant type and a second well having a second dopant type different from the first dopant type,
the second opening is over the second well and a third well having the first dopant type,
a portion of the second masking layer blocking the first opening is over the first well and the second well, and
a portion of the second masking layer blocking the second opening is over the second well and the third well.

### Claim 20 (depends on 19)

The method of claim 19, wherein the forming the first contact plug and the second contact plug comprises:
forming the first contact plug and the second contact plug over the second well;
forming a third contact plug in the first opening over the first well; and
forming a fourth contact plug in the second opening over the third well.