# US 10,770,446 B2 · Semiconductor packages and methods of manufacturing the same

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- Number: US 10,770,446 B2
- Document ID: US10770446B2
- Status: Granted
- Kind: B2
- Application number: 16/201,021
- Filed: 2018-11-27
- Published: 2019-03-28
- Granted: 2020-09-08
- Earliest claimed: 2016-03-02
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Young Lyong Kim; Jin-woo Park; Choongbin Yim; Younji Min
- Web page: https://patentgrep.com/patent/US10770446B2

## CPC

- H10W 90/00: Package configurations
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/655: Fan-out layouts
- H10W 70/656: Fan-in layouts
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/072: {of bump connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/10: characterised by their shape or disposition
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, an interconnect substrate spaced apart from the semiconductor chip on the substrate and including a conductive member therein, a solder ball on the interconnect substrate and electrically connected to the conductive member, a polymer layer on the interconnect substrate and the semiconductor chip and including an opening through which the solder ball is exposed, and polymer particles in the solder ball and including the same material as the polymer layer.

## Claims

### Claim 1

A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip on the redistribution substrate;
a conductive member spaced apart from the semiconductor chip on the redistribution substrate;
a solder ball on the conductive member and electrically connected to the conductive member;
a polymer layer between the semiconductor chip and the conductive member on the redistribution substrate, the polymer layer having an opening through which the solder ball is exposed, and a residue on the solder ball and including the same material as the polymer layer, wherein a bottom surface of the solder ball is disposed at a higher level than a bottom surface of the semiconductor chip.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, further comprising a polymer particle in the solder ball.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, wherein the polymer particle comprising the same material as the polymer layer.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, further comprising a solder pad between the conductive member and the solder ball,
wherein the solder ball has a melting point less than that of the solder pad.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, further comprising an interconnect substrate comprising:
base layers stacked on the redistribution substrate; and
the conductive member in the base layers.

### Claim 6 (depends on 5)

The semiconductor package of claim 5, wherein the semiconductor chip is surrounded by and spaced apart from the interconnect substrate in a plan view.

### Claim 7

A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip on the redistribution substrate;
a conductive member spaced apart from the semiconductor chip on the redistribution substrate;
a solder ball on the conductive member and electrically connected to the conductive member; and
a polymer layer between the semiconductor chip and the conductive member on the redistribution substrate, the polymer layer having an opening through which the solder ball is exposed,
wherein a bottom surface of the solder ball is disposed at a higher level than a bottom surface of the semiconductor chip,
wherein the redistribution substrate comprises:
a first insulation pattern on the bottom surface of the semiconductor chip, a bottom surface of the conductive member, and a lowermost surface of the polymer layer; and
a redistribution member on a bottom surface of the first insulation pattern and having a melting point of more than that of the solder ball.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, the polymer layer comprising:
a first polymer layer covering the semiconductor chip; and
a second polymer layer on an upper surface of the first polymer layer,
wherein the solder ball is disposed on the upper surface of the first polymer layer.

### Claim 9 (depends on 8)

The semiconductor package of claim 8, further comprising:
a polymer particle in the solder ball and comprising the same material as the second polymer layer; and
wherein the opening is provided in the second polymer layer.

### Claim 10 (depends on 8)

The semiconductor package of claim 8, further comprising:
an interconnect vias provided in the first polymer layer and connected to the conductive member; and
an interconnect pattern provided on the upper surface of the first polymer layer and electrically connected to the solder ball,
wherein the solder ball is not aligned with the conductive member in a vertical direction.

### Claim 11 (depends on 1)

The semiconductor package of claim 1, further comprising an upper package on the polymer layer and electrically connected to the solder ball.

### Claim 12

A semiconductor package, comprising:
a substrate;
a semiconductor chip on a center region of the substrate; a conductive member on an edge region of the substrate; a solder ball on the conductive member and electrically connected to the conductive member;
a polymer layer between the semiconductor chip and the conductive member on the substrate, the polymer layer having an opening through which the solder ball is exposed; and residue polymer particles in the solder ball and including the same material as the polymer layer.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein a bottom surface of the solder ball is disposed at a higher level than a top surface of the semiconductor chip.

### Claim 14 (depends on 12)

The semiconductor package of claim 12, wherein the solder ball has a melting point less than that of the conductive member.

### Claim 15 (depends on 12)

The semiconductor package of claim 12, further comprising an interconnect substrate comprising:
base layers stacked on the substrate; and
the conductive member in the base layers,
wherein the interconnect substrate comprises a hole penetrating thereinside, and
wherein the semiconductor chip is provided in the hole of the interconnect substrate.

### Claim 16 (depends on 12)

The semiconductor package of claim 12, the substrate comprising:
a first insulation pattern on a bottom surface of the semiconductor chip, a bottom surface of the conductive member, and a lowermost surface of the polymer layer; and
a redistribution member on a bottom surface of the first insulation pattern have a melting point of more than that of the solder ball,
wherein the redistribution member is electrically connected to a chip pad of the semiconductor chip and the conductive member.

### Claim 17 (depends on 12)

The semiconductor package of claim 12, the polymer layer comprising:
a first polymer layer covering the semiconductor chip; and
a second polymer layer on an upper surface of the first polymer layer,
wherein the solder ball is disposed on the upper surface of the first polymer layer.

### Claim 18 (depends on 1)

The semiconductor package of claim 1 wherein the bottom surface of the solder ball is disposed at a higher level than a top surface of the semiconductor chip.