# US 10,770,445 B2 · Methods of fabricating semiconductor packages including reinforcement top die

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- Number: US 10,770,445 B2
- Document ID: US10770445B2
- Status: Granted
- Kind: B2
- Application number: 16/176,806
- Filed: 2018-10-31
- Published: 2019-08-22
- Granted: 2020-09-08
- Earliest claimed: 2018-02-19
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Kwon Whan Han
- Web page: https://patentgrep.com/patent/US10770445B2

## CPC

- H10W 74/014: {using batch processing}
- H10W 90/00: Package configurations
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 72/0198: {batch processes}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 74/016: {using moulds}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10P 72/7416: {used during dicing or grinding}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 72/07204: {using temporary auxiliary members, e.g. sacrificial coatings}
- H10W 72/07304: {the auxiliary member being temporary, e.g. a sacrificial coating}
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/07354: {changes in dispositions}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of fabricating semiconductor packages may include forming stack structures on a base die wafer, disposing a top die wafer on the stack structures, and forming a molding layer filling a space between the base die wafer and the top die wafer.

## Claims

### Claim 1

A method of fabricating semiconductor packages, the method comprising:
forming stack structures on a base die wafer;
disposing a top die wafer on the stack structures; and
forming a molding layer filling a space between the base die wafer and the top die wafer,
wherein the stack structures are comprised of core dies,
wherein the base die wafer includes base die regions in which integrated circuits are realized and a peripheral region between the base die regions; and
wherein the stack structures overlap with the base die regions, respectively, in a plan view,
further comprising removing the peripheral region of the base die wafer, a portion of the molding layer overlapping with the peripheral region, and a portion of the top die wafer overlapping with the peripheral region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the top die wafer has a thickness which is greater than a thickness of the base die wafer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the top die wafer has a thickness which is greater than a thickness of each of the core dies.

### Claim 4 (depends on 1)

The method of claim 1, wherein the top die wafer is a dummy silicon wafer.

### Claim 5 (depends on 1)

The method of claim 1, wherein each of the base die regions further includes first through vias that substantially penetrate the base die region.

### Claim 6 (depends on 5)

The method of claim 5,
wherein each of the core dies further includes second through vias that substantially penetrate the core die; and
wherein the second through vias are electrically connected to the first through vias.

### Claim 7

A method of fabricating semiconductor packages, the method comprising:
forming stack structures on a base die wafer;
disposing a top die wafer on the stack structures; and
forming a molding layer filling a space between the base die wafer and the top die wafer,
wherein the stack structures are comprised of core dies,
wherein the base die wafer includes base die regions in which integrated circuits are realized and a peripheral region between the base die regions;
wherein the stack structures overlap with the base die regions, respectively, in a plan view,
wherein the core dies are memory semiconductor dies; and
wherein each of the base die regions is a logic semiconductor die in which a controller device for controlling the memory semiconductor dies is integrated.

### Claim 8

A method of fabricating semiconductor packages, the method comprising:
forming stack structures on a base die wafer;
disposing a top die wafer having a trench, which is opened toward the base die wafer, on the stack structures; and
forming a molding layer filling a space between the base die wafer and the top die wafer,
wherein the base die wafer includes base die regions in which integrated circuits are realized and a peripheral region between the base die regions;
wherein the stack structures overlap with the base die regions, respectively, in a plan view; and
wherein the trench of the top die wafer is disposed to overlap with the peripheral region of the base die wafer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the top die wafer has a thickness which is greater than a thickness of the base die wafer.

### Claim 10 (depends on 8)

The method of claim 8, wherein the stack structures are comprised of core dies.

### Claim 11 (depends on 10)

The method of claim 10, wherein the top die wafer has a thickness which is greater than a thickness of each of the core dies.

### Claim 12 (depends on 8)

The method of claim 8, wherein the molding layer extends to have a filling portion that fills the trench of the top die wafer overlapping with the peripheral region of the base die wafer, and
the method further comprises reducing a thickness of the top die wafer to expose a top surface of the filling portion of the molding layer after forming the molding layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein the top die wafer is divided into top dies which are isolated from each other by the filling portion if the top surface of the filling portion is exposed.

### Claim 14 (depends on 12)

The method of claim 12, further comprising removing the peripheral region of the base die wafer, a portion of the molding layer overlapping with the peripheral region, and a portion of the filling portion of the molding layer overlapping with the peripheral region.

### Claim 15 (depends on 8)

The method of claim 8, wherein the trench of the top die wafer has a width which is greater than a width of the peripheral region of the base die wafer.