# US 10,770,440 B2 · Micro-LED display assembly

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- Number: US 10,770,440 B2
- Document ID: US10770440B2
- Status: Granted
- Kind: B2
- Application number: 15/459,336
- Filed: 2017-03-15
- Published: 2018-09-20
- Granted: 2020-09-08
- Earliest claimed: 2017-03-15
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Luke England; Bartlomiej Jan Pawlak
- Web page: https://patentgrep.com/patent/US10770440B2

## CPC

- H10W 90/00: Package configurations
- H10H 29/142: {Two-dimensional arrangements, e.g. asymmetric LED layout}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/60: wherein the TFTs are in active matrices
- H10H 20/818: within the light-emitting regions
- H10H 20/821: of the light-emitting regions, e.g. non-planar junctions
- H10H 20/825: containing nitrogen, e.g. GaN
- H10H 20/857: Interconnections, e.g. lead-frames, bond wires or solder balls
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure relates to semiconductor structures and, more particularly, to a micro-light emitting diode (LED) display assembly and methods of manufacture. The structure includes an interposer and a plurality of micro-LED arrays each of which include a plurality of through-vias connecting pixels of the plurality of micro-LED arrays to the interposer.

## Claims

### Claim 1

A structure, comprising:
an interposer;
a plurality of light emitting diode (LED) arrays each of which comprise a plurality of pixels composed of multiple sub-pixels;
a plurality of through-vias composed of an insulator liner, diffusion barrier metal and electroplated metallization feature, each through via of the plurality of through-vias being directly below and connecting to each pixel of the plurality of pixels of each of the plurality of LED arrays by a metal pad that is in physical contact and directly below the each pixel, wherein each through via of the plurality of through vias is further connected to the interposer and a single through via is used per pixel; and
a horizontal plate composed of GaN, wherein the plurality of pixels share the horizontal plate composed of GaN from above the plurality of pixels.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the interposer is a silicon interposer with driver circuits.

### Claim 3 (depends on 1)

The structure of claim 1, wherein the interposer is a glass interposer.

### Claim 4 (depends on 1)

The structure of claim 1, wherein the through-vias are through silicon vias.

### Claim 5 (depends on 4)

The structure of claim 4, wherein each of the pixels is connected to the interposer by a separate one of the through silicon vias.

### Claim 6 (depends on 1)

The structure of claim 1, wherein the pixels are composed of GaN and the through-vias are copper through silicon vias integrated into a same die as the pixels.

### Claim 7 (depends on 1)

The structure of claim 1, wherein the through-vias are connected to the interposer by pillars which match a pitch of the through-vias.

### Claim 8 (depends on 1)

The structure of claim 1, wherein the plurality of LED arrays are equally spaced apart on the interposer.

### Claim 9 (depends on 8)

The structure of claim 8, wherein an across die pixel pitch is equal to a pixel pitch within each of the plurality of LED arrays.

### Claim 10 (depends on 1)

The structure of claim 1, wherein a diameter of the through vias is about ½ a pixel pitch.

### Claim 11 (depends on 1)

The structure of claim 1, further comprising a back-end of the line wiring scheme which is interposed between the interposer and the plurality of LED arrays, the back-end of the line wiring scheme connects the each of the plurality of through-vias of each of the pixels to the interposer by separate pillars aligned with each of the plurality of through-vias of each of the pixels.

### Claim 12

A structure comprising:
an interposer comprising a plurality of through vias;
a plurality of light emitting diode (LED) arrays each of which comprises a plurality of pixels, a plurality of through-vias composed of an insulator liner, a barrier metal and electroplated metallization feature and each one of the plurality of through vias being directly below and connecting a separate pixel of the plurality of pixels by a metal pad that is directly below and in physical contact with the separate pixel, and wherein each pixel of the plurality of pixels is composed of multiple sub-pixels;
a back-end of the line wiring scheme which is positioned between and connected to the interposer and the plurality of LED arrays by a plurality of pillars, wherein each pillar of the plurality of pillars is aligned with and connects to the separate pixel of the plurality of pixels by a respective one of the plurality of through-vias such that only a single pillar the single pixel, respectively; and
a horizontal plate composed of GaN, wherein the plurality of pixels share the horizontal plate composed of GaN from above the plurality of pixels.

### Claim 13 (depends on 12)

The structure of claim 12, wherein:
the plurality of LED arrays are equally spaced apart; and
an across die pixel pitch is equal to a pixel pitch within each of the plurality of -LED arrays.

### Claim 14 (depends on 13)

The structure of claim 13, wherein the pixels are composed of GaN and the through-vias of the plurality of the plurality of LED arrays are copper through silicon vias integrated into a same die as the pixels.

### Claim 15 (depends on 14)

The structure of claim 14, wherein the through silicon vias are connected to the back end of the-line wiring scheme by the pillars.

### Claim 16 (depends on 15)

The structure of claim 15, wherein the pillars are solder connections.

### Claim 17 (depends on 15)

The structure of claim 15, wherein the pillars match a pitch of the through silicon vias.

### Claim 18 (depends on 14)

The structure of claim 14, wherein a diameter of each through-via is about ½ a pixel pitch.

### Claim 19 (depends on 12)

The structure of claim 12, wherein the back-end of the line interposer is a silicon interposer with driver circuits.

### Claim 20 (depends on 12)

The structure of claim 12, wherein the back-end of the line interposer is a glass interposer.