# US 10,770,437 B2 · Semiconductor package and manufacturing method of the same

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- Number: US 10,770,437 B2
- Document ID: US10770437B2
- Status: Granted
- Kind: B2
- Application number: 16/100,002
- Filed: 2018-08-09
- Published: 2018-12-06
- Granted: 2020-09-08
- Earliest claimed: 2016-06-17
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Jui-Pin Hung; Feng-Cheng Hsu; Shuo-Mao Chen; Shin-Puu Jeng
- Web page: https://patentgrep.com/patent/US10770437B2

## CPC

- H10W 90/00: Package configurations
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/016: {using moulds}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 72/01: {Manufacture or treatment}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/354: {comprising polymers}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/20: Configurations of stacked chips
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a semiconductor package, including a first layer, a second layer, and a conductive array. The first layer includes a packaged die having a carrier surface and a molding surface, and a first die structure in proximity to the carrier surface. An active region of the first die structure is electrically coupled to the packaged die through a solder. The second layer includes a second die structure, the second die structure being connected to the active region of the first die structure by a first redistributed layer (RDL). The conductive array is connected to an active region of the second die structure by a second RDL. The present disclosure also provides a method for manufacturing the aforesaid semiconductor package.

## Claims

### Claim 1

A method for manufacturing a semiconductor package, comprising:
forming a bottom redistribution layer (RDL) over a glass substrate;
forming a through insulator via (TIV) over the bottom RDL;
flip-chip bonding a first die over the bottom RDL;
molding the first die and the TIV;
forming an upper RDL over the first die;
flip-chip bonding a second die over the upper RDL;
forming a solder on the upper RDL and laterally surrounds the second die;
stacking a third packaged die over the second die and electrically connecting the third packaged die to the first die through soldering; and
forming an underfill surrounding the second die and the solder;
wherein the third packaged die having a carrier and a molding on the carrier, the carrier comprising a carrier surface and the molding comprising a molding surface, and the solder is in contact with the carrier surface of the third packaged die.

### Claim 2 (depends on 1)

The method of claim 1, further comprising debonding the glass substrate from the bottom RDL.

### Claim 3 (depends on 1)

The method of claim 1, further comprising etching back a debonded surface and exposing a conductive contact.

### Claim 4 (depends on 3)

The method of claim 3, further comprising disposing a solder ball over the conductive contact.

### Claim 5 (depends on 4)

The method of claim 4, further comprising disposing a third die at the same level of the solder ball.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first die comprises a plurality of dies having different thicknesses.

### Claim 7 (depends on 1)

The method of claim 1, wherein the second die comprises a plurality of dies having different thicknesses.

### Claim 8

A method for manufacturing a semiconductor package, comprising:
forming a bottom redistribution layer (RDL) over a glass substrate;
forming a first conductive bump over the bottom RDL;
bonding a first die on the bottom RDL, the first die having a top surface coplanar with the first conductive bump;
forming an upper RDL over the first die;
forming a second conductive bump over the upper RDL;
bonding a second die on the upper RDL; and
stacking a third packaged die over the second die and electrically connecting the third packaged die to the first die through a solder bump;
forming an underfill surrounding the second die, the second conductive bump, and a portion of the solder bump.

### Claim 9 (depends on 8)

The method of claim 8, wherein stacking the third packaged die over the second die comprises an alignment operation and a reflow operation.

### Claim 10 (depends on 9)

The method of claim 9, wherein the alignment operation comprises aligning the solder bump with the second conductive bump.

### Claim 11 (depends on 8)

The method of claim 8, wherein forming the underfill is subsequent to stacking the third packaged die over the second die.

### Claim 12 (depends on 8)

The method of claim 8, wherein forming the underfill is prior to stacking the third packaged die over the second die.

### Claim 13 (depends on 8)

The method of claim 8, wherein the second conductive bump comprises a smaller height than that of the first conductive bump.

### Claim 14 (depends on 8)

The method of claim 8, wherein the first die comprises a plurality of dies having different thicknesses.

### Claim 15

A method for manufacturing a semiconductor package, comprising:
forming a bottom redistribution layer (RDL) over a glass substrate;
forming a conductive plug over the bottom RDL;
bonding a first die on the bottom RDL, the first die having a top surface coplanar with the conductive plug;
forming an upper RDL over the first die;
bonding a second die on the upper RDL;
stacking a third packaged die over the second die and electrically connecting the third packaged die to the first die through a conductive bump, a solder bump, the upper RDL and the bottom RDL; and
forming an underfill surrounding the second die, the conductive bump, and a portion of the solder bump.

### Claim 16 (depends on 15)

The method of claim 15, wherein stacking the third packaged die over the second die comprises disposing the solder bump of the third packaged die over the upper RDL.

### Claim 17 (depends on 15)

The method of claim 15, further comprising forming the conductive bump over the upper RDL prior to bonding the second die over the upper RDL.

### Claim 18 (depends on 17)

The method of claim 17, wherein stacking the third packaged die over the second die comprises aligning the solder bump of the third packaged die to the conductive bump over the upper RDL.

### Claim 19 (depends on 15)

The method of claim 15, further comprising molding the first die and the conductive plug prior to forming the upper RDL.

### Claim 20 (depends on 15)

The method of claim 15, wherein a top surface of the second die is higher than the two conductive bumps.