# US 10,770,433 B1 · High bandwidth die to die interconnect with package area reduction

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- Number: US 10,770,433 B1
- Document ID: US10770433B1
- Status: Granted
- Kind: B1
- Application number: 16/287,635
- Filed: 2019-02-27
- Published: 2020-08-27
- Granted: 2020-09-08
- Earliest claimed: 2019-02-27
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Chonghua Zhong; Jun Zhai; Kunzhong Hu
- Web page: https://patentgrep.com/patent/US10770433B1

## CPC

- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 90/00: Package configurations
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 76/47: Solid or gel fillings
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/01: {Manufacture or treatment}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07354: {changes in dispositions}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/341: {Dispositions of die-attach connectors, e.g. layouts}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/354: {comprising polymers}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/853: {On the same surface}
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

## Claims

### Claim 1

A package structure comprising:
a first wiring layer including a first side and a second side opposite the first side;
a first die and a vertical interposer side-by-side on the first side of the first wiring layer, wherein the vertical interposer includes electrical interconnects from a first side of the vertical interposer coupled with the first side of the first wiring layer to a second side of the vertical interposer opposite the first side of the vertical interposer;
a second die face down on and electrically connected with the second side of the vertical interposer; and
a local interposer on the second side of the first wiring layer and in electrical connection with the first die and the vertical interposer;
wherein the second die occupies a larger area than both the vertical interposer and the local interposer.

### Claim 2 (depends on 1)

The package structure of claim 1, wherein the local interposer includes a plurality of terminals on a first side of the local interposer that is coupled with the second side of the first wiring layer, and the local interposer does not include a terminal on a second side of the local interposer opposite the first side of the local interposer.

### Claim 3 (depends on 1)

The package structure of claim 1, wherein the first die occupies a larger area than the second die.

### Claim 4 (depends on 3)

The package structure of claim 3, wherein the first die and the second die comprise split logic.

### Claim 5 (depends on 3)

The package structure of claim 3, wherein first transistors of the first die are formed with a smaller processing node than second transistors of the second die.

### Claim 6 (depends on 1)

The package structure of claim 1, further comprising a mechanical chiplet attached to the first die laterally adjacent to the second die.

### Claim 7 (depends on 1)

The package structure of claim 1, wherein the vertical interposer is hybrid bonded with the second die.

### Claim 8 (depends on 1)

The package structure of claim 1, wherein solder bumps electrically connect the vertical interposer with the second die.

### Claim 9

A package structure comprising:
a first wiring layer including a first side and a second side opposite the first side;
a first die and a vertical interposer side-by-side on the first side of the first wiring layer, wherein the vertical interposer includes electrical interconnects from a first side of the vertical interposer coupled with the first side of the first wiring layer to a second side of the vertical interposer opposite the first side of the vertical interposer;
a second die face down on and electrically connected with the second side of the vertical interposer;
a local interposer on the second side of the first wiring layer and in electrical connection with the first die and the vertical interposer;
a first molding compound encapsulating the first die, the vertical interposer, and the second die; and
a second molding compound encapsulating the local interposer on the second side of the first wiring layer.

### Claim 10 (depends on 9)

The package structure of claim 9, further comprising a mechanical chiplet attached to the first die laterally adjacent to the second die.

### Claim 11 (depends on 9)

The package structure of claim 9, further comprising a first plurality of conductive pillars extending from the first wiring layer and through the first molding compound.

### Claim 12 (depends on 9)

The package structure of claim 9, wherein first transistors of the first die are formed with a smaller processing node than second transistors of the second die.

### Claim 13 (depends on 9)

The package structure of claim 9, further comprising a second plurality of conductive pillars extending from the first wiring layer and through the second molding compound.

### Claim 14 (depends on 13)

The package structure of claim 13, further comprising a second wiring layer on the second molding compound and connected to the second plurality of conductive pillars.

### Claim 15 (depends on 14)

The package structure of claim 14, wherein the second wiring layer is on a planarized surface including the second molding compound, the second plurality of conductive pillars, and the local interposer.

### Claim 16 (depends on 13)

The package structure of claim 13, further comprising a second package on and in electrical connection with the first plurality of conductive pillars.

### Claim 17 (depends on 13)

The package structure of claim 13, further comprising a plurality of solder bumps that electrically connect the second wiring layer to a package routing substrate.

### Claim 18

A method of forming a package structure comprising:
placing a second die and mechanical chiplet on a carrier substrate;
bonding a vertical interposer to the second die;
placing a first die on the second die and the mechanical chiplet;
encapsulating the second die, the mechanical chiplet, the vertical interposer, and the first die in a first molding compound;
mounting a local interposer on and in electrical connection with the vertical interposer and the first die; and
encapsulating the local interposer in a second molding compound.

### Claim 19 (depends on 18)

The method of claim 18, wherein bonding the vertical interposer to the second die comprises hybrid bonding.

### Claim 20 (depends on 18)

The method of claim 18, wherein bonding the vertical interposer to the second die comprises solder bumping.