# US 10,770,427 B1 · Chip package structure and method for forming the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,770,427 B1
- Document ID: US10770427B1
- Status: Granted
- Kind: B1
- Application number: 16/454,435
- Filed: 2019-06-27
- Granted: 2020-09-08
- Earliest claimed: 2019-06-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Ling-Wei Li; Jung-Hua Chang; Cheng-Lin Huang
- Web page: https://patentgrep.com/patent/US10770427B1

## CPC

- H10W 72/072: {of bump connectors}
- H10W 20/042: {the barrier, adhesion or liner layers being seed or nucleation layers}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/484: {Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/016: {using moulds}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/655: Fan-out layouts
- H10W 72/019: {of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/354: {comprising polymers}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/014: {using batch processing}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a chip package structure is provided. The method includes forming a conductive via structure in a first substrate. The method includes bonding a chip to a first surface of the first substrate. The method includes forming a barrier layer over a second surface of the first substrate. The method includes forming a first insulating layer over the barrier layer. The method includes forming a conductive pad over the first insulating layer and in the first opening, the second opening, and the third opening. The conductive pad continuously extends from the conductive via structure into the third opening. The method includes forming a conductive bump over the conductive pad in the third opening.

## Claims

### Claim 1

A method for forming a chip package structure, comprising:
forming a conductive via structure in a first substrate;
bonding a chip to a first surface of the first substrate;
forming a barrier layer over a second surface of the first substrate, wherein the barrier layer is in direct contact with the first substrate, and the barrier layer has a first opening exposing the conductive via structure;
forming a first insulating layer over the barrier layer, wherein the first insulating layer has a second opening and a third opening, the second opening is over the first opening and exposes the conductive via structure, the third opening partially exposes the barrier layer, and the barrier layer is thinner than the first insulating layer;
forming a conductive pad over the first insulating layer and in the first opening, the second opening, and the third opening, wherein the conductive pad continuously extends from the conductive via structure into the third opening; and
forming a conductive bump over the conductive pad in the third opening.

### Claim 2 (depends on 1)

The method for forming the chip package structure as claimed in claim 1, further comprising:
bonding the first substrate to a second substrate through the conductive bump.

### Claim 3 (depends on 1)

The method for forming the chip package structure as claimed in claim 1, wherein the conductive bump is thicker than the conductive pad, and the conductive bump is in direct contact with the conductive pad.

### Claim 4 (depends on 1)

The method for forming the chip package structure as claimed in claim 1, wherein a bottom portion of the conductive bump is in the third opening.

### Claim 5 (depends on 1)

The method for forming the chip package structure as claimed in claim 1, wherein the second opening further exposes a portion of the barrier layer.

### Claim 6 (depends on 1)

The method for forming the chip package structure as claimed in claim 1, wherein the conductive bump and the conductive via structure are misaligned in a vertical direction perpendicular to the second surface.

### Claim 7 (depends on 1)

The method for forming the chip package structure as claimed in claim 1, further comprising:
after forming the conductive bump over the conductive pad in the third opening, forming a second insulating layer over the first insulating layer and the conductive pad, wherein the second insulating layer surrounds the conductive bump.

### Claim 8 (depends on 1)

The method for forming the chip package structure as claimed in claim 1, wherein a first width of the conductive pad is greater than a sum of a second width of the conductive bump, a third width of the conductive via structure, and a distance between the conductive bump and the conductive via structure.

### Claim 9 (depends on 1)

The method for forming the chip package structure as claimed in claim 1, wherein the forming of the conductive bump comprises:
forming a mask layer over the conductive pad and the first insulating layer, wherein the mask layer is in direct contact with the conductive pad and the first insulating layer, and the mask layer has a fourth opening exposing the conductive pad in the third opening;
forming the conductive bump in the fourth opening; and
removing the mask layer.

### Claim 10 (depends on 1)

The method for forming the chip package structure as claimed in claim 1, wherein the barrier layer and the first insulating layer are made of different materials.

### Claim 11

A method for forming a chip package structure, comprising:
forming a conductive via structure in a substrate;
bonding a chip to a first surface of the substrate;
forming a barrier layer over a second surface of the substrate, wherein the barrier layer is in direct contact with the substrate;
forming a first insulating layer partially over the barrier layer;
forming a conductive pad over the first insulating layer, wherein the conductive pad has a first portion and a second portion, the first portion passes through the barrier layer and the first insulating layer to connect with the conductive via structure, and the second portion passes through the first insulating layer and is in direct contact with the barrier layer;
forming a second insulating layer over the first insulating layer and the conductive pad; and
forming a conductive bump over the second insulating layer, wherein a first bottom portion of the conductive bump passes through the second insulating layer to connect with the second portion of the conductive pad.

### Claim 12 (depends on 11)

The method for forming the chip package structure as claimed in claim 11, further comprising:
before forming the conductive bump over the second insulating layer, forming a seed layer over the second insulating layer, wherein a second bottom portion of the seed layer passes through the second insulating layer to conformally cover the second portion of the conductive pad, and the conductive bump is formed over the seed layer.

### Claim 13 (depends on 12)

The method for forming the chip package structure as claimed in claim 12, wherein the second bottom portion of the seed layer is partially in the first insulating layer.

### Claim 14 (depends on 11)

The method for forming the chip package structure as claimed in claim 11, wherein the conductive pad has a W-like shape in a cross-sectional view of the conductive pad.

### Claim 15 (depends on 11)

The method for forming the chip package structure as claimed in claim 11, wherein the barrier layer is harder than the first insulating layer.

### Claim 16

A chip package structure, comprising:
a first substrate;
a conductive via structure passing through the first substrate;
a chip over a first surface of the first substrate;
a barrier layer over a second surface of the first substrate, wherein the barrier layer is in direct contact with the first substrate;
a first insulating layer over the barrier layer;
a conductive pad over the first insulating layer, wherein the conductive pad has a first portion and a second portion, the first portion passes through the barrier layer and the first insulating layer to connect with the conductive via structure, and the second portion passes through the first insulating layer and is in direct contact with the barrier layer; and
a conductive bump over the second portion of the conductive pad.

### Claim 17 (depends on 16)

The chip package structure as claimed in claim 16, wherein the conductive bump is thicker than the conductive pad, and the conductive bump is in direct contact with the conductive pad.

### Claim 18 (depends on 17)

The chip package structure as claimed in claim 17, wherein a contact area between the conductive bump and the conductive pad is greater than an area of a top surface of the conductive bump.

### Claim 19 (depends on 16)

The chip package structure as claimed in claim 16, further comprising:
a second insulating layer over the first insulating layer and the first portion of the conductive pad.

### Claim 20 (depends on 16)

The chip package structure as claimed in claim 16, further comprising:
a second insulating layer over the first insulating layer and the conductive pad, wherein the conductive bump passes through the second insulating layer to connect with the conductive pad, and the second insulating layer is partially between the conductive bump and the conductive pad.