# US 10,770,418 B2 · Fan-out semiconductor package

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- Number: US 10,770,418 B2
- Document ID: US10770418B2
- Status: Granted
- Kind: B2
- Application number: 15/916,785
- Filed: 2018-03-09
- Published: 2018-07-12
- Granted: 2020-09-08
- Earliest claimed: 2016-08-31
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Da Hee Kim; Young Gwan Ko
- Web page: https://patentgrep.com/patent/US10770418B2

## CPC

- H10W 72/90: Bond pads, in general
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/652: Cross-sectional shapes
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 70/654: Top-view layouts
- H10W 70/655: Fan-out layouts
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/00: Package configurations
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; a resin layer disposed on the encapsulant; and a rear redistribution layer embedded in the encapsulant so that one surface thereof is exposed by the encapsulant, wherein the resin layer covers at least portions of the exposed one surface of the rear redistribution layer, and the rear redistribution layer is electrically connected to the redistribution layer of the first connection member through connection members formed in first openings penetrating through the resin layer and the encapsulant.

## Claims

### Claim 1

A semiconductor package comprising:
a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least a portion of the inactive surface of the semiconductor chip;
a second connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip;
a rear redistribution layer including a conductor layer embedded in the encapsulant and a seed layer disposed on the conductor layer and being thinner than the conductor layer, a portion of the encapsulant disposed between the rear redistribution layer and the second connection member;
a resin layer disposed on the encapsulant and being in contact with the seed layer of the rear redistribution layer and the encapsulant; and
a conductive connection member penetrating through the resin layer, the rear redistribution layer, and the encapsulant, the conductive connection member contacting exposed side surfaces of the resin layer.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the resin layer includes openings exposing at least portions of a surface of the rear redistribution layer.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the conductive connection member further contacts exposed side surfaces of the rear redistribution layer.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein the conductive connection member includes a solder or a metal paste.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, further comprising a first connection member disposed on the second connection member and having a through-hole,
wherein the semiconductor chip is disposed in the through-hole of the first connection member, and
the encapsulant encapsulates at least portions of the first connection member.

### Claim 6 (depends on 5)

The semiconductor package of claim 5, wherein the rear redistribution layer is electrically connected to a redistribution layer of the first connection member through the conductive connection member.

### Claim 7 (depends on 5)

The semiconductor package of claim 5, wherein the first connection member includes a first insulating layer, a first redistribution layer contacting the second connection member and embedded in the first insulating layer, and a second redistribution layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first redistribution layer is embedded, and
the first and second redistribution layers of the first connection member are electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member.

### Claim 8 (depends on 7)

The semiconductor package of claim 7, wherein the first connection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer, and
the third redistribution layer is electrically connected to the connection pads.

### Claim 9 (depends on 7)

The semiconductor package of claim 7, wherein a distance between the redistribution layer of the second connection member and the first redistribution layer is greater than that between the redistribution layer of the second connection member and the connection pads.

### Claim 10 (depends on 7)

The semiconductor package of claim 7, wherein the first redistribution layer has a thickness greater than that of the redistribution layer of the second connection member.

### Claim 11 (depends on 7)

The semiconductor package of claim 7, wherein a lower surface of the first redistribution layer is disposed on a level above a lower surface of the connection pads.

### Claim 12 (depends on 5)

The semiconductor package of claim 5, wherein the first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer respectively disposed on opposite surfaces of the first insulating layer, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, a third redistribution layer disposed on the second insulating layer, a third insulating layer disposed on the first insulating layer and covering the second redistribution layer, and a fourth redistribution layer disposed on the third insulating layer, and
the first to fourth redistribution layers are electrically connected to the connection pads.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein a lower surface of the third redistribution layer is disposed on a level below a lower surface of the connection pads.

### Claim 14 (depends on 1)

The semiconductor package of claim 1, further comprising a passivation layer disposed on the second connection member and including openings exposing the redistribution layer of the second connection member
wherein at least one of the openings of the passivation layer is disposed in a fan-out region.

### Claim 15

A semiconductor package comprising:
a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
a second connection member disposed on the active surface of the semiconductor chip;
a resin layer, the semiconductor chip disposed between the resin layer and the second connection member; and
a rear redistribution layer protruding from the resin layer and including a conductor layer embedded in an encapsulant and a seed layer disposed on the conductor layer and being thinner than the conductor layer, the semiconductor chip disposed between the rear redistribution layer and the second connection member; and
a conductive connection member penetrating through the resin layer, the rear redistribution layer, and the encapsulant, the conductive connection member contacting exposed side surfaces of the resin layer,
wherein a portion of the encapsulant and a portion of the rear redistribution layer are disposed between the resin layer and the inactive surface of the semiconductor chip, the resin layer being in contact the seed layer of with the rear redistribution layer and the encapsulant.

### Claim 16 (depends on 15)

The semiconductor package of claim 15, further comprising a first connection member disposed on the second connection member and having a through-hole
wherein the semiconductor chip is disposed in the through-hole of the first connection member the encapsulant encapsulates at least portions of the first connection member,
the rear redistribution layer is electrically connected to a redistribution layer of the first connection member through the conductive connection member formed in openings penetrating through the resin layer and the encapsulant
the redistribution layer of the first connection member is electrically connected to the connection pads of the semiconductor chip through a redistribution layer of the second connection member.

### Claim 17

A semiconductor package comprising:
a first connection member having a through-hole;
semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating portions of the first connection member and the inactive surface of the semiconductor chip,
a second connection member facing the active surface and disposed on the first connection member and the semiconductor chip;
a rear redistribution layer embedded in the encapsulant and facing the inactive surface of the semiconductor chip;
a resin layer being in contact with the rear redistribution layer; and
conductive connection members at least partially filling first openings penetrating through the resin layer, the rear redistribution layer, and the encapsulant, the conductive connection members contacting exposed side surfaces of the resin layer and exposed side surfaces of the rear redistribution layer.

### Claim 18 (depends on 17)

The semiconductor package of claim 17 wherein the conductive connection members do not fill second openings penetrating only through the resin layer.