# US 10,770,413 B2 · Chip packaging structure and method, and electronic device

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- Number: US 10,770,413 B2
- Document ID: US10770413B2
- Status: Granted
- Kind: B2
- Application number: 16/168,169
- Filed: 2018-10-23
- Published: 2019-03-14
- Granted: 2020-09-08
- Earliest claimed: 2017-09-14
- Assignees: Shenzhen Goodix Technology Co., Ltd.
- Applicants: Shenzhen Goodix Technology Co., Ltd.
- Inventors: Baoquan Wu; Xinfei Yu
- Web page: https://patentgrep.com/patent/US10770413B2

## CPC

- H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60)
- H10W 70/464: {Additional interconnections in combination with leadframes}
- H10W 70/465: {Bumps or wires}
- H10W 70/468: {Circuit boards}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 70/417: {Bonding materials between chips and die pads}
- H10W 72/07553: {changes in shapes}
- H10W 72/354: {comprising polymers}
- H10W 72/537: {Multiple bond wires having different shapes}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/10: characterised by their shape or disposition
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/755: {between a chip and a laterally-adjacent insulating package substrate, interpose or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A chip packaging structure and method, and an electronic device, are provided. The chip packaging structure includes a support, a chip, at least one conductor, and a package for plastic packaging the support, the chip and the conductor. The chip is arranged on an upper surface of the support, a chip pad is formed on the upper surface of the chip, and the chip pad is connected to an external pad of the support by a bonding wire. The conductor is connected to the external pad or a ground pad of the chip pad, and the shortest distance from the conductor to the upper surface of the package is less than the shortest distance from the bonding wire to the upper surface of the package, whereby chip failure caused by static electricity discharge is greatly reduced.

## Claims

### Claim 1

A chip packaging structure, comprising:
a support;
a chip;
at least one conductor; and
a package for plastic packaging the support, the chip, and the conductor;
the chip being disposed on an upper surface of the support, a chip pad being formed on an upper surface of the chip, and the chip pad being connected to an external pad of the support by a bonding wire;
the conductor being connected to a ground pad of the chip pad, and a shortest distance from the conductor to an upper surface of the package being less than a shortest distance from the bonding wire to the upper surface of the package; and
the conductor comprising a first end and a second end which are two free ends located oppositely in a length of the conductor, the first end being connected to the ground pad of the chip pad, the second end extending towards the upper surface of the package, and an end surface of the second end being covered with the package.

### Claim 2 (depends on 1)

The chip packaging structure according to claim 1, wherein a difference between a shortest distance from the bonding wire to the upper surface of the package and a shortest distance from the conductor to the upper surface of the package is greater than or equal to 10 μm.

### Claim 3 (depends on 1)

The chip packaging structure according to claim 1, wherein the conductor comprises a metal block.

### Claim 4 (depends on 1)

An electronic device, comprising the chip packaging structure according to claim 1.

### Claim 5

A chip packaging method, comprising:
disposing a chip on an upper surface of a support, and connecting a chip pad on an upper surface of the chip to an external pad of the support by a bonding wire;
connecting at least one conductor to a ground pad of the chip pad, and a maximum distance from the conductor to the support being greater than a maximum distance from the bonding wire to the support;
packaging the support, the chip and the conductor to form a package;
wherein a shortest distance from the conductor to the upper surface of the package is less than a shortest distance from the bonding wire to the upper surface of the package; and
wherein the conductor comprises a first end and a second end which are two free ends located oppositely in a length of the conductor, the first end is connected to the ground pad of the chip pad, the second end extends towards the upper surface of the package, and an end surface of the second end being covered with the package.

### Claim 6 (depends on 5)

The chip packaging method according to claim 5, wherein a difference between a shortest distance from the bonding wire to the upper surface of the package and a shortest distance from the conductor to the upper surface of the package is greater than or equal to 10 μm.

### Claim 7 (depends on 5)

The chip packaging method according to claim 5, wherein the conductor comprises a metal block.

### Claim 8 (depends on 1)

The chip packaging structure according to claim 1, wherein the second end of the conductor is located right above the chip.

### Claim 9 (depends on 5)

The chip packaging structure according to claim 5, wherein the second end of the conductor is located right above the chip.

### Claim 10

A chip packaging structure, comprising:
a support;
a chip;
at least one conductor; and
a package for plastic packaging the support, the chip, and the conductor;
the chip being disposed on an upper surface of the support, a chip pad being formed on an upper surface of the chip, and the chip pad being connected to an external pad of the support by a bonding wire;
the conductor being connected to a ground pad of the chip pad and comprising a crest portion disposed closer to an upper surface of the package than any other portions of the conductor, and the crest portion being covered with the package; and
the distance from the crest portion to the upper surface of the package being less than a shortest distance from the bonding wire to the upper surface of the package.

### Claim 11 (depends on 10)

The chip packaging structure according to claim 10, wherein the conductor comprises a metal wire, a first end of the metal wire is connected to the ground pad of the chip pad, and a second end of the metal wire is connected to the external pad.

### Claim 12 (depends on 11)

The chip packaging structure according to claim 11, wherein the metal wire has a diameter greater than or equal to 0.5 mil.

### Claim 13 (depends on 10)

The chip packaging structure according to claim 10, wherein a difference between a shortest distance from the bonding wire to the upper surface of the package and a shortest distance from the conductor to the upper surface of the package is greater than or equal to 10 μm.

### Claim 14 (depends on 10)

The chip packaging structure according to claim 10, wherein the conductor comprises a metal block.

### Claim 15 (depends on 13)

The chip packaging structure according to claim 13, wherein the second end of the conductor is located right above the chip.