# US 10,770,406 B2 · Methods and apparatus for scribe street pads with reduced die chipping during wafer dicing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,406 B2 - Document ID: US10770406B2 - Status: Granted - Kind: B2 - Application number: 15/820,176 - Filed: 2017-11-21 - Published: 2018-03-29 - Granted: 2020-09-08 - Earliest claimed: 2016-05-31 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Ricky Alan Jackson; Erika Lynn Mazotti; Sudtida Lavangkul - Web page: https://patentgrep.com/patent/US10770406B2 ## CPC - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads} - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W 74/147: {the encapsulations being multilayered} - H10W 46/503: {Located in scribe lines} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed. ## Claims ### Claim 1 A semiconductor wafer, comprising: a plurality of scribe streets arranged in rows and columns and having saw kerf lanes defined in a central portion and running parallel with the scribe streets; a plurality of probe pads each formed centered in the scribe streets and intersected by the saw kerf lanes, each probe pad further including: a lower level conductor layer having an outside border portion coextensive with the outside edge of the probe pad and an opening in a center portion; and an upper level conductor layer forming two portions of upper level conductor layer material on only two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane. ### Claim 2 (depends on 1) The semiconductor wafer of claim 1, in which for ones of the plurality of probe pads located in the scribe streets but not in an intersection of scribe streets, the saw kerf lane does not intersect any portion of an upper level conductor layer. ### Claim 3 (depends on 1) The semiconductor wafer of claim 1, and further including: a passivation layer overlying the top surface of the semiconductor wafer; an opening in the passivation layer coextensive with the probe pad; and an upper surface layer covering the surface of the opening in the probe pad, including a conductive layer deposited in the opening and covering the uppermost surface of the upper conductive layer. ### Claim 4 (depends on 1) The semiconductor wafer of claim 1, in which the coverage of the upper level conductor layer is less than about twenty percent. ### Claim 5 (depends on 1) The semiconductor wafer of claim 1, in which the upper level conductor layer further includes copper. ### Claim 6 (depends on 1) The semiconductor wafer of claim 1, in which the upper level conductor layer is arranged as islands of upper level conductor material. ### Claim 7 (depends on 1) The semiconductor wafer of claim 1 in which the upper level conductor layer is arranged as narrow rails of upper level conductor material. ### Claim 8 (depends on 1) The semiconductor wafer of claim 1, in which the lower level conductor layer further includes aluminum. ### Claim 9 (depends on 1) The semiconductor wafer of claim 1, in which the lower level conductor layer has a coverage that is less than or equal to about thirty percent. ### Claim 10 (depends on 1) The semiconductor wafer of claim 1, and further including a first level conductor layer formed below the lower level conductor layer, the first level conductor layer forming a rectangular pad region located in a central portion of the probe pad. ### Claim 11 (depends on 10) The semiconductor wafer of claim 10, and further including member portions of the lower level conductor layer across the opening in the central portion, and vias connecting the member portions of the lower level conductor layer to the rectangular pad region of the first level conductor layer. ### Claim 12 A semiconductor wafer, comprising: a plurality of scribe streets arranged in rows and columns and having saw kerf lanes defined in a central portion and running parallel with the scribe streets; a plurality of probe pads each formed centered in the scribe streets and intersected by the saw kerf lanes, each probe pad further including: a plurality of lower level conductor layers each having an outside border portion coextensive with the outside edge of the probe pad and an opening in a center portion; and a plurality of upper level conductor layers each forming two portions of upper level conductor layer material on only two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane. ### Claim 13 (depends on 12) The semiconductor wafer of claim 12, in which for ones of the plurality of probe pads located in the scribe streets but not in an intersection of scribe streets, the saw kerf lane does not intersect any portion of an upper level conductor layers. ### Claim 14 (depends on 12) The semiconductor wafer of claim 12, and further including: a passivation layer overlying the top surface of the semiconductor wafer, an opening in the passivation layer coextensive with the probe pad; and an upper surface layer covering the surface of the opening in the probe pad, including a conductive layer deposited in the opening and covering the uppermost surface of the upper conductive layer. ### Claim 15 (depends on 14) The semiconductor wafer of claim 14, in which the coverage of the upper level conductor layers is less than about twenty percent. ### Claim 16 (depends on 15) The semiconductor wafer of claim 15, in which the upper level conductor layers further include copper. ### Claim 17 (depends on 15) The semiconductor wafer of claim 15, in which the lower level conductor layers further include aluminum. ### Claim 18 (depends on 15) The semiconductor wafer of claim 15, in which the lower level conductor layers have a coverage that is less than or equal to about thirty percent. ### Claim 19 (depends on 15) The semiconductor wafer of claim 15, and further including a first level conductor layer formed below the lower level conductor layers, the first level conductor layer forming a rectangular pad region located in a central portion of the probe pad. ### Claim 20 (depends on 19) The semiconductor wafer of claim 19, and further including member portions of the lower level conductor layers across the opening in the central portion, and vias connecting the member portions of the lower level conductor layers to the rectangular pad region of the first level conductor layer. ### Claim 21 A semiconductor wafer, comprising: a plurality of scribe streets arranged in rows and columns and having saw kerf lanes defined in a central portion and running parallel with the scribe streets; a plurality of probe pads each formed centered in the scribe streets and intersected by the saw kerf lanes, each probe pad further including: a lower level conductor layer having an outside border portion coextensive with the outside edge of the probe pad and an opening in a center portion; and an upper level conductor layer forming portions of upper level conductor layer material on outer edges of the probe pad, the portions spaced from, and only on opposite sides of the saw kerf lane. ### Claim 22 (depends on 21) The semiconductor wafer of claim 21, in which for ones of the plurality of probe pads located in the scribe streets but not in an intersection of scribe streets, the saw kerf lane does not intersect any portion of an upper level conductor layer. ### Claim 23 (depends on 21) The semiconductor wafer of claim 21, and further including: a passivation layer overlying the top surface of the semiconductor wafer, an opening in the passivation layer coextensive with the probe pad; and an upper surface layer covering the surface of the opening in the probe pad, including a conductive layer deposited in the opening and covering the uppermost surface of the upper conductive layer. ### Claim 24 (depends on 21) The semiconductor wafer of claim 21, and further including a first level conductor layer formed below the lower level conductor layer, the first level conductor layer forming a rectangular pad region located in a central portion of the probe pad. ### Claim 25 (depends on 24) The semiconductor wafer of claim 24, and further including member portions of the lower level conductor layer across the opening in the central portion, and vias connecting the member portions of the lower level conductor layer to the rectangular pad region of the first level conductor layer. ### Claim 26 A semiconductor wafer, comprising: a plurality of scribe streets arranged in rows and columns and having saw kerf lanes defined in a central portion and running parallel with the scribe streets; a plurality of probe pads each formed centered in the scribe streets and intersected by the saw kerf lanes, each probe pad further including: a plurality of lower level conductor layers each having an outside border portion coextensive with the outside edge of the probe pad and an opening in a center portion; and a plurality of upper level conductor layers each forming portions of upper level conductor layer material on outer edges of the probe pad, the portions spaced from, and only on opposite sides of the saw kerf lane. ### Claim 27 (depends on 26) The semiconductor wafer of claim 26, in which for ones of the plurality of probe pads located in the scribe streets but not in an intersection of scribe streets, the saw kerf lane does not intersect any portion of an upper level conductor layers. ### Claim 28 (depends on 26) The semiconductor wafer of claim 26, and further including: a passivation layer overlying the top surface of the semiconductor wafer; an opening in the passivation layer coextensive with the probe pad; and an upper surface layer covering the surface of the opening in the probe pad, including a conductive layer deposited in the opening and covering the uppermost surface of the upper conductive layer. ### Claim 29 (depends on 28) The semiconductor wafer of claim 28, and further including a first level conductor layer formed below the lower level conductor layers, the first level conductor layer forming a rectangular pad region located in a central portion of the probe pad. ### Claim 30 (depends on 29) The semiconductor wafer of claim 29, and further including member portions of the lower level conductor layers across the opening in the central portion, and vias connecting the member portions of the lower level conductor layers to the rectangular pad region of the first level conductor layer.