# US 10,770,404 B2 · Shielding for through-silicon-via noise coupling > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,404 B2 - Document ID: US10770404B2 - Status: Granted - Kind: B2 - Application number: 16/220,236 - Filed: 2018-12-14 - Published: 2019-04-25 - Granted: 2020-09-08 - Earliest claimed: 2013-03-12 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Jaw-Juinn Horng; Chung-Peng Hsieh - Web page: https://patentgrep.com/patent/US10770404B2 ## CPC - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/217: {comprising ring-shaped isolation structures outside of the via holes} - H10W 20/43: Layouts of interconnections - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 90/00: Package configurations - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract In some embodiments, an integrated circuit device includes a semiconductor substrate. An active area is disposed in the semiconductor substrate. A first guard ring is disposed in the semiconductor substrate and entirely surrounds the active area. The first guard ring has a first conductivity type. A via penetrates through the semiconductor substrate and is spaced apart from the active area such that the via is disposed outside of the first guard ring. A second guard ring is disposed in the semiconductor substrate and entirely surrounds the via and the first guard ring. The second guard ring has the first conductivity type and is disjoint from the first guard ring. ## Claims ### Claim 1 A method of shielding to prevent signals carried by a through substrate via from causing noise in an active area of an integrated circuit, comprising: forming a first guard ring around a first area comprising the through substrate via, wherein the first guard ring has a first conductivity type; and forming a second guard ring around a second area comprising the active area, wherein the second guard ring has the first conductivity type; wherein the through substrate via is outside of the second area fully surrounded by the second guard ring, wherein the active area is outside of the first area fully surrounded by the first guard ring, and wherein the active area is directly between a first portion of the second guard ring and a second portion of the second guard ring, wherein the first portion of the second guard ring is directly between the active area and the through substrate via, and wherein the first portion of the second guard ring has a first thickness greater than a second thickness of the second portion of the second guard ring. ### Claim 2 (depends on 1) The method of claim 1, wherein: the first guard ring operates as a first ground having a first noise characteristic; and the second guard ring operates as a second ground having a second noise characteristic, wherein the first noise characteristic is different from the second noise characteristic. ### Claim 3 (depends on 1) The method of claim 1, wherein the first and second guard rings are grounded to a common ground pad. ### Claim 4 (depends on 1) The method of claim 1, wherein the through substrate via is directly between a first portion of the first guard ring and a second portion of the first guard ring, wherein the first portion of the first guard ring is directly between the active area and the through substrate via, and wherein the first portion of the first guard ring has a first thickness that is about equal to a second thickness of the second portion of the first guard ring. ### Claim 5 (depends on 1) The method of claim 1, wherein the first guard ring comprises a width of at least 0.25 μm between the through substrate via and the active area. ### Claim 6 (depends on 1) The method of claim 1, wherein the first and second guard rings reduce a noise coupling coefficient between the through substrate via and the active area at 3 GHz circuit operating frequency to −60 dB or less. ### Claim 7 (depends on 6) The method of claim 6, wherein the through substrate via and the active area are no more than 50 μm apart. ### Claim 8 (depends on 1) The method of claim 1, wherein the active area has a surface area of at least 100 pmt. ### Claim 9 An integrated circuit device, comprising: a semiconductor body; an active area disposed in the semiconductor body; a via penetrating through the semiconductor body without passing through the active area; a first contiguous region throughout which the semiconductor body is doped to at least a first concentration of a first doping type, the first contiguous region surrounding an area of the semiconductor body comprising the active area; and a second contiguous region throughout which the semiconductor body is doped to at least the first concentration of the first doping type, the second contiguous region surrounding the via, the second contiguous region being disjoint from the first contiguous region; wherein the semiconductor body is not doped to the first doping type or is doped to a second concentration of the first doping type that is less than the first concentration; wherein the via is outside the area surrounded by the first contiguous region; and wherein the via is directly between a first portion of the second contiguous region and a second portion of the second contiguous region, wherein the first portion of the second contiguous region is directly between the via and the active area, and wherein the first portion of the second contiguous region has a first thickness greater than a second thickness of the second portion of the second contiguous region. ### Claim 10 (depends on 9) The integrated circuit device of claim 9, wherein the second contiguous region fully surrounds the first contiguous region. ### Claim 11 (depends on 10) The integrated circuit device of claim 10, wherein the first portion of the second contiguous region divides a total area encompassed by the second contiguous region into first and second mutually exclusive sub-areas, wherein a first sub-area surrounds the via, and wherein a second sub-area surrounds both the first contiguous region and the active area. ### Claim 12 (depends on 11) The integrated circuit device of claim 11, wherein the first sub-area is smaller than the second sub-area. ### Claim 13 (depends on 9) The integrated circuit device of claim 9, wherein the active area is formed within a well that is doped with a second doping type, wherein the second doping type is different than the first doping type. ### Claim 14 (depends on 9) The integrated circuit device of claim 9, wherein the first contiguous region is at least 0.10 μm wide around the active area. ### Claim 15 An integrated circuit device, comprising: a semiconductor body; an active area disposed in the semiconductor body; a via penetrating through the semiconductor body without passing through the active area; a first contiguous region throughout which the semiconductor body is doped to at least a first concentration of a first doping type, the first contiguous region surrounding an area of the semiconductor body comprising the active area; and a second contiguous region throughout which the semiconductor body is doped to at least the first concentration of the first doping type, the second contiguous region surrounding the via, the second contiguous region being disjoint from the first contiguous region; wherein the semiconductor body is not doped to the first doping type or is doped to a second concentration of the first doping type that is less than the first concentration; wherein the via is outside the area surrounded by the first contiguous region; and wherein the active area is directly between a first portion of the first contiguous region and a second portion of the first contiguous region, wherein the first portion of the first contiguous region is directly between the active area and the via, and wherein the first portion of the first contiguous region has a first thickness greater than a second thickness of the second portion of the first contiguous region. ### Claim 16 (depends on 15) The integrated circuit device of claim 15, wherein a first minimum distance between the via and the second contiguous region is less than a second minimum distance between the via and the first contiguous region. ### Claim 17 (depends on 15) The integrated circuit device of claim 15, wherein the via and the active area are no more than 35 μm apart. ### Claim 18 (depends on 15) The integrated circuit device of claim 15, wherein the via is directly between a first portion of the second contiguous region and a second portion of the second contiguous region, wherein the first portion of the second contiguous region is directly between the via and the active area, and wherein the first portion of the second contiguous region has a first thickness that is about equal to a second thickness of the second portion of the second contiguous region. ### Claim 19 (depends on 15) The integrated circuit device of claim 15, wherein the second contiguous region fully surrounds the first contiguous region. ### Claim 20 (depends on 15) The integrated circuit device of claim 15, wherein the second thickness of the second portion of the first contiguous region is at least equal to 0.10 μm.