# US 10,770,403 B2 · Fan-out semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,403 B2 - Document ID: US10770403B2 - Status: Granted - Kind: B2 - Application number: 16/197,764 - Filed: 2018-11-21 - Published: 2019-11-07 - Granted: 2020-09-08 - Earliest claimed: 2018-05-04 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Mi Ja Han; Han Kim; Seong Chan Park - Web page: https://patentgrep.com/patent/US10770403B2 ## CPC - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 42/284: {shielding resins} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/611: {for connecting multiple chips together} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 90/00: Package configurations - H10W 70/6528: {of the portions that connect to chips, wafers or package parts} - H10W 70/666: {Organic materials or pastes} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/9413: {on encapsulations} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A fan-out semiconductor package includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, an encapsulant encapsulating the semiconductor chip, and an electromagnetic radiation blocking layer disposed above the semiconductor chip and including a base layer in which a plurality of degassing holes are formed and a porous blocking portion filled in the plurality of degassing holes. ## Claims ### Claim 1 A fan-out semiconductor package comprising: a connection member including an insulating layer and a redistribution layer; a semiconductor chip disposed on the connection member; an encapsulant encapsulating the semiconductor chip; and an electromagnetic radiation blocking layer disposed above the semiconductor chip and including a base layer in which a plurality of degassing holes are formed and a porous blocking portion filled in the plurality of degassing holes. ### Claim 2 (depends on 1) The fan-out semiconductor package of claim 1, wherein the porous blocking portion has a form in which a plurality of particles are agglomerated. ### Claim 3 (depends on 1) The fan-out semiconductor package of claim 1, wherein the porous blocking portion is a porous plating layer. ### Claim 4 (depends on 1) The fan-out semiconductor package of claim 1, wherein the base layer comprises metal thin film. ### Claim 5 (depends on 1) The fan-out semiconductor package of claim 1, wherein the base layer comprises a Cu plating layer. ### Claim 6 (depends on 1) The fan-out semiconductor package of claim 1, wherein the electromagnetic radiation blocking layer includes a first region and a second region, and a density of the degassing holes is higher in the first region than in the second region. ### Claim 7 (depends on 6) The fan-out semiconductor package of claim 6, wherein the second region is disposed in a region corresponding to the semiconductor chip. ### Claim 8 (depends on 6) The fan-out semiconductor package of claim 6, further comprising a core member including a through-hole in which the semiconductor chip is accommodated and a metal layer covering walls forming the through-hole. ### Claim 9 (depends on 8) The fan-out semiconductor package of claim 8, wherein the metal layer of the core member and the electromagnetic radiation blocking layer are connected to each other by a conductive via penetrating through the encapsulant. ### Claim 10 (depends on 6) The fan-out semiconductor package of claim 6, further comprising a plurality of passive components disposed on the connection member. ### Claim 11 (depends on 10) The fan-out semiconductor package of claim 10, wherein the first region is disposed in a region corresponding to at least some of the plurality of passive components. ### Claim 12 (depends on 11) The fan-out semiconductor package of claim 11, wherein distances from upper surfaces of at least some of the plurality of passive components to an upper surface of the encapsulant are different from each other, and a density of the degassing holes is higher in a region corresponding to a passive component having a larger distance from an upper surface thereof to the upper surface of the encapsulant among the plurality of passive components, the upper surfaces being surfaces of corresponding components and encapsulant away from the connection member. ### Claim 13 (depends on 10) The fan-out semiconductor package of claim 10, wherein the plurality of passive components include a capacitor and an inductor, and a density of the degassing holes is higher in a region corresponding to the capacitor than in a region corresponding to the inductor. ### Claim 14 A fan-out semiconductor package comprising: a connection member including an insulating layer and a redistribution layer; a semiconductor chip disposed on the connection member; an encapsulant encapsulating the semiconductor chip; and an electromagnetic radiation blocking layer disposed above the semiconductor chip and having a porous structure. ### Claim 15 (depends on 14) The fan-out semiconductor package of claim 14, wherein the electromagnetic radiation blocking layer has a form in which a plurality of particles are agglomerated. ### Claim 16 (depends on 14) The fan-out semiconductor package of claim 14, wherein the electromagnetic radiation blocking layer is a porous plating layer.