# US 10,770,399 B2 · Semiconductor package having a filled conductive cavity > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,399 B2 - Document ID: US10770399B2 - Status: Granted - Kind: B2 - Application number: 16/274,991 - Filed: 2019-02-13 - Published: 2020-08-13 - Granted: 2020-09-08 - Earliest claimed: 2019-02-13 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Chee Yang Ng; Hock Siang Chua; Stefan Macheiner; Josef Maerz; Nurfarena Othman; Joseph Victor Soosai Prakasam; Hong Hock Tay - Web page: https://patentgrep.com/patent/US10770399B2 ## CPC - H10W 40/228: {the projecting parts being wire-shaped or pin-shaped} - H10W 70/65: Shapes or dispositions of interconnections - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 40/258: {Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)} - H10W 70/095: {of vias therein} - H10W 70/098: {Applying pastes or inks, e.g. screen printing (H10W70/095 takes precedence)} - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 70/66: Conductive materials thereof - H10W 70/68: Shapes or dispositions thereof - H10W 70/695: Organic materials - H10W 74/114: {by a substrate and the encapsulations} - H10W 90/00: Package configurations - H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping} - H10W 72/07236: {Soldering or alloying} - H10W 72/073: {of die-attach connectors} - H10W 72/07336: {Soldering or alloying} - H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 72/265: {Providing thermal transfer, e.g. thermal bumps} - H10W 72/267: {Multiple bump connectors having different functions} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/536: {the connected ends being ball-shaped} - H10W 72/5363: {the connected ends being wedge-shaped} - H10W 72/5366: {the bond wires having kinks} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/01: Manufacture or treatment - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a frame having an insulative body with a first main surface and a second main surface opposite the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulative body. A thermally and/or electrically conductive material filling the first cavity in the insulative body and having a different composition than the first plurality of metal traces. The thermally and/or electrically conductive material provides a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body. A semiconductor die attached to the frame at the first main surface of the insulative body is electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body. A corresponding method of manufacture is also described. ## Claims ### Claim 1 A semiconductor package, comprising: a frame comprising an insulative body having a first main surface and a second main surface opposite the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulative body; a thermally and/or electrically conductive material filling the first cavity in the insulative body and having a different composition than the first plurality of metal traces, the thermally and/or electrically conductive material providing a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body; and a semiconductor die attached to the frame at the first main surface of the insulative body and electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body, wherein the semiconductor die is a power semiconductor die, wherein a high-power terminal of the power semiconductor die facing the first main surface of the insulative body is electrically connected to the thermally and/or electrically conductive material filling the first cavity in the insulative body. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the frame further comprises one or more second metal traces at the second main surface of the insulative body and one or more vias electrically connecting one or more metal traces of the first plurality of metal traces at the first main surface of the insulative body to the one or more second metal traces at the second main surface of the insulative body, and wherein the high-power terminal of the power semiconductor die is electrically connected to a metal trace at the second main surface of the insulative body through the thermally and/or electrically conductive material filling the first cavity in the insulative body. ### Claim 3 (depends on 2) The semiconductor package of claim 2, wherein the thermally and/or electrically conductive material filling the first cavity has an area which is at least 10× the average area of the individual vias. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein the frame further comprises a second cavity in the insulative body, wherein the second cavity is smaller than and laterally spaced apart from the first cavity, wherein the second cavity is filled with a thermally and/or electrically conductive material having a different composition than the first plurality of metal traces and providing a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body, and wherein a second high-power terminal of the power semiconductor die facing the first main surface of the insulative body is electrically connected to the thermally and/or electrically conductive material filling the second cavity in the insulative body. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein the power semiconductor die comprises one or more low power terminals electrically connected to one or more second metal traces at the second main surface of the insulative body through one or more vias and one or more of the first plurality of metal traces. ### Claim 6 (depends on 1) The semiconductor package of claim 1, further comprising a logic die attached to a side of the power semiconductor die facing away from the frame or to the frame at the first main surface of the insulative body, wherein the logic die is configured to control the power semiconductor die. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein the thermally and/or electrically conductive material filling the first cavity comprises a hardened silver paste, a hardened copper paste, a nanocarbon material, or a hardened solder paste, and wherein the first plurality of metal traces comprise electroplated copper. ### Claim 8 A method of manufacturing a semiconductor package, the method comprising: forming a cavity in an insulative body of a frame, the insulative body having a first main surface and a second main surface opposite the first main surface, and a first plurality of metal traces at the first main surface of the insulative body; filling the first cavity in the insulative body with a thermally and/or electrically conductive material having a different composition than the first plurality of metal traces, the electrically conductive material providing a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body; and attaching a semiconductor die to the frame at the first main surface of the insulative body so that the semiconductor die is electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body, wherein attaching the semiconductor die to the frame at the first main surface of the insulative body comprises: flip-chip bonding a high-power terminal of the semiconductor die to the thermally and/or electrically conductive material filling the first cavity in the insulative body and a plurality of low power terminals of the semiconductor die to interconnect pads formed in the plurality of metal traces at the first main surface of the insulative body. ### Claim 9 (depends on 8) The method of claim 8, wherein filling the first cavity in the insulative body with the thermally and/or electrically conductive material comprises: screen printing an electrically conductive paste in the first cavity and on the interconnect pads. ### Claim 10 (depends on 9) The method of claim 9, wherein the electrically conductive paste is a silver paste, a copper paste, or a solder paste, and wherein the first plurality of metal traces is formed by electrochemical deposition prior to the screen printing of the electrically conductive paste. ### Claim 11 A semiconductor package, comprising: a frame comprising an insulative body having a first main surface and a second main surface opposite the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulative body; a thermally and/or electrically conductive material filling the first cavity in the insulative body and having a different composition than the first plurality of metal traces, the thermally and/or electrically conductive material providing a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body; and a semiconductor die attached to the frame at the first main surface of the insulative body and electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body, wherein the thermally and/or electrically conductive material filling the first cavity is not covered by a metal trace at the first main surface of the insulative body, wherein the semiconductor die is attached to the thermally and/or electrically conductive material at the first main surface of the insulative body, wherein the first cavity terminates at a metal trace at the second main surface of the insulative body, wherein the semiconductor die is electrically connected to the metal trace that terminates the first cavity at the second main surface of the insulative body through the thermally and/or electrically conductive material filling the first cavity. ### Claim 12 A semiconductor package, comprising: a frame comprising an insulative body having a first main surface and a second main surface opposite the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulative body; a thermally and/or electrically conductive material filling the first cavity in the insulative body and having a different composition than the first plurality of metal traces, the thermally and/or electrically conductive material providing a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body; and a semiconductor die attached to the frame at the first main surface of the insulative body and electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body, wherein the first cavity terminates at a metal trace at the first main surface of the insulative body, wherein the semiconductor die is attached to the metal trace that terminates the first cavity at the first main surface of the insulative body, wherein the semiconductor die is electrically connected to the thermally and/or electrically conductive material filling the first cavity through the metal trace that terminates the first cavity at the first main surface of the insulative body. ### Claim 13 (depends on 12) The semiconductor package of claim 12, wherein the thermally and/or electrically conductive material filling the first cavity is not covered by a metal trace at the second main surface of the insulative body. ### Claim 14 (depends on 12) The semiconductor package of claim 12, wherein the semiconductor die is encapsulated in a mold compound at the first main surface of the insulative body, and wherein the metal trace that terminates the first cavity at the first main surface of the insulative body separates the mold compound from the thermally and/or electrically conductive material filling the first cavity. ### Claim 15 A semiconductor package, comprising: a frame comprising an insulative body having a first main surface and a second main surface opposite the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulative body; a thermally and/or electrically conductive material filling the first cavity in the insulative body and having a different composition than the first plurality of metal traces, the thermally and/or electrically conductive material providing a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body; and a semiconductor die attached to the frame at the first main surface of the insulative body and electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body, wherein the frame further comprises a second cavity in the insulative body, wherein the second cavity is smaller than and laterally spaced apart from the first cavity, wherein the second cavity is filled with a thermally and/or electrically conductive material having a different composition than the first plurality of metal traces and providing a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body, wherein the semiconductor die is electrically connected to the thermally and/or electrically conductive material filling the second cavity in the insulative body. ### Claim 16 (depends on 15) The semiconductor package of claim 15, wherein the thermally and/or electrically conductive material filling the second cavity has the same composition as the thermally and/or electrically conductive material filling the first cavity. ### Claim 17 (depends on 15) The semiconductor package of claim 15, wherein the thermally and/or electrically conductive material filling the first cavity comprises a hardened silver paste, a hardened copper paste, a nanocarbon material, or a hardened solder paste, wherein the first plurality of metal traces comprises electroplated copper, and wherein the thermally and/or electrically conductive material filling the second cavity comprises a hardened silver paste, a hardened copper paste, a nanocarbon material, or a hardened solder paste.