# US 10,770,398 B2 · Graphics processing unit and high bandwidth memory integration using integrated interface and silicon interposer

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- Number: US 10,770,398 B2
- Document ID: US10770398B2
- Status: Granted
- Kind: B2
- Application number: 16/180,538
- Filed: 2018-11-05
- Published: 2020-05-07
- Granted: 2020-09-08
- Earliest claimed: 2018-11-05
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Chan H. Yoo; Owen R. Fay
- Web page: https://patentgrep.com/patent/US10770398B2

## CPC

- H10W 70/611: {for connecting multiple chips together}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07253: {changes in shapes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/237: {Multiple bump connectors having different shapes}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device assembly that includes a second side of an interposer being connected to a first side of a substrate. A plurality of interconnects may be connected to a second side of the substrate. First and second semiconductor devices are connected directly to the first side of the interposer. The interposer is configured to enable the first semiconductor device and the second semiconductor device to communicate with each other through the interposer. The interposer may be a silicon interposer that includes complementary metal-oxide-semiconductor circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes attaching both a memory device and a processing unit directly to a first side of an interposer and connecting a second side of the interposer to a substrate.

## Claims

### Claim 1

A semiconductor device assembly comprising:
a substrate having a first side and a second side;
an interposer having a first side and a second side, the second side of the interposer connected to the first side of the substrate, wherein the interposer comprises complementary metal-oxide-semiconductor circuits;
a plurality of electrical interconnects connected to the second side of the substrate;
a first semiconductor device connected directly to the first side of the interposer;
a second semiconductor device connected directly to the first side of the interposer, wherein the interposer is configured to enable the first semiconductor device and the second semiconductor device to communicate with each other through the interposer;
wherein the first semiconductor device is a processing unit;
wherein the second semiconductor device is a memory device; and
wherein the plurality of complementary metal-oxide-semiconductor circuits provide a buffer for data transfer between the first semiconductor device and the second semiconductor device.

### Claim 2 (depends on 1)

The semiconductor device assembly of claim 1, wherein the interposer is a substrate comprised of silicon.

### Claim 3 (depends on 2)

The semiconductor device assembly of claim 2, wherein the substrate comprises a laminated substrate.

### Claim 4 (depends on 3)

The semiconductor device assembly of claim 3, wherein the processing unit further comprises a graphics processing unit (GPU) or a central processing unit (CPU).

### Claim 5 (depends on 4)

The semiconductor device assembly of claim 4, further comprising a third semiconductor device connected directly to the first side of the interposer, wherein the third semiconductor device is a memory device and wherein the interposer is configured to enable the GPU or CPU and the third semiconductor device to communicate with each other through the interposer.

### Claim 6 (depends on 5)

The semiconductor device assembly of claim 5, wherein the interposer enables communication between the laminated substrate and the GPU or CPU and enables communication between the laminated substrate and the memory device.

### Claim 7 (depends on 1)

The semiconductor device assembly of claim 1, wherein the plurality of complementary metal-oxide-semiconductor circuits provides logic to control data transfer between the first semiconductor device and the second semiconductor device.

### Claim 8 (depends on 1)

The semiconductor device assembly of claim 1, wherein the memory device further comprises a high bandwidth memory device.

### Claim 9

A semiconductor device assembly comprising:
a substrate having a first side and a second side;
a silicon interposer having a first side and a second side, the second side of the interposer connected to the first side of the substrate, the silicon interposer having complementary metal-oxide-semiconductor circuits;
a graphics processing unit (GPU) or central processing unit (CPU) connected directly to the first side of the interposer;
a plurality of memory devices connected directly to the first side of the interposer, wherein the silicon interposer is configured to enable the GPU or CPU and the plurality of memory devices communicate with each other through the silicon interposer; and
wherein the complementary metal-oxide-semiconductor circuits provide a buffer for data transfer between the GPU or CPU and the plurality of memory devices.

### Claim 10 (depends on 9)

The semiconductor device assembly of claim 9, wherein the substrate is a printed circuit board.

### Claim 11 (depends on 10)

The semiconductor device assembly of claim 10, wherein the plurality of memory devices comprises at least two high bandwidth memory devices.

### Claim 12

A method of making a semiconductor device assembly comprising:
attaching a memory device directly onto a first side of an interposer;
attaching a processing unit directly onto the first side of the interposer;
attaching a second side of the interposer to a first side of a substrate, wherein the processing unit and the memory device are configured to communicate with each other through the interposer; and
applying complementary metal-oxide-semiconductor processing to the interposer before attaching the memory device directly onto the first side of the interposer to form complementary metal-oxide-semiconductor circuits, wherein the complementary metal-oxide-semiconductor circuits provide a buffer for data transfer between the processing unit and the memory device.

### Claim 13 (depends on 12)

The method of claim 12, comprising attaching a second memory device directly to the first side of the interposer and wherein the substrate comprises a printed circuit board.

### Claim 14

A method of making a semiconductor device assembly comprising:
attaching a plurality of memory devices directly onto a first side of an interposer wafer;
attaching a plurality of individual processing units onto the first side of the interposer wafer;
processing the interposer wafer to form a plurality of individual semiconductor device assemblies each comprising at least one semiconductor device and an individual processing unit;
attaching a second side of an individual semiconductor device assembly to a first side of a substrate; and
applying complementary metal-oxide-semiconductor processing to the interposer wafer prior to attaching the plurality of semiconductor devices onto a first side of an interposer wafer to form complementary metal-oxide semiconductor circuits, wherein the complementary metal-oxide-semiconductor circuits provide a buffer for data transfer between the plurality of individual processing units and the plurality of memory devices.

### Claim 15 (depends on 14)

The method of claim 14, comprising providing a wafer having the plurality of graphics processing units connected to a side of the wafer and processing the wafer to form the plurality of individual processing units.

### Claim 16 (depends on 15)

The method of claim 15, wherein the individual processing units comprise graphics processing units or central processing units.

### Claim 17 (depends on 16)

The method of claim 16, attaching a plurality of solder balls to a second side of the substrate.