# US 10,770,396 B2 · Semiconductor structure and method for fabricating the same

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- Number: US 10,770,396 B2
- Document ID: US10770396B2
- Status: Granted
- Kind: B2
- Application number: 16/235,013
- Filed: 2018-12-28
- Published: 2020-07-02
- Granted: 2020-09-08
- Earliest claimed: 2018-12-28
- Assignees: Vanguard International Semiconductor Corporation
- Applicants: Vanguard International Semiconductor Corporation
- Inventors: Fang-Ming Lee; Sheng-Wei Fu; Chung-Yeh Lee
- Web page: https://patentgrep.com/patent/US10770396B2

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/378: {Contact regions to the substrate regions}
- H10D 64/111: {Field plates}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/036: {the barrier, adhesion or liner layers being within a main fill metal}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a substrate, an epitaxial layer disposed on the substrate, a conductive feature disposed in the epitaxial layer having a protruding portion that is higher than the epitaxial layer, and a diffusion barrier layer disposed on sidewalls of the conductive feature.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate;
an epitaxial layer disposed on the substrate;
a conductive feature disposed in the epitaxial layer and having a protruding portion that is higher than the epitaxial layer;
a diffusion barrier layer disposed on sidewalls of the conductive feature, wherein the diffusion barrier layer comprises a barrier oxide layer, wherein a bottom surface of the conductive feature is in direct contact with the epitaxial layer; and
a source region disposed in the epitaxial layer, wherein the diffusion barrier layer contacts the source region and separates the source region from the conductive feature.

### Claim 2 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein a width of the protruding portion is greater than a width of the conductive feature in the epitaxial layer.

### Claim 3 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the protruding portion covers a top surface of the diffusion barrier layer.

### Claim 4 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the diffusion barrier layer comprises one or more than one dielectric barrier layers.

### Claim 5 (depends on 4)

The semiconductor structure as claimed in claim 4, wherein the diffusion barrier layer further comprises a barrier nitride layer on the barrier oxide layer.

### Claim 6 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the conductive feature is disposed between two laterally diffused metal oxide semiconductors (LDMOSs) and the conductive feature penetrates a common source region of the LDMOSs, wherein each of the two laterally diffused metal oxide semiconductors comprises a gate structure disposed between a drain region and the common source region.

### Claim 7 (depends on 6)

The semiconductor structure as claimed in claim 6, further comprising:
an insulating layer disposed on an upper surface of the gate structure and the epitaxial layer, wherein the insulating layer exposes the conductive feature, the common source region, and a portion of the drain region; and
a conductive layer disposed continuously on the upper surface of the gate structure, the common source region, and the conductive feature.

### Claim 8

A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming an epitaxial layer on the substrate;
forming a mask structure on the epitaxial layer, and the mask structure has an opening exposing a portion of the epitaxial layer;
using the mask structure as an etching mask to remove the exposed portion of the epitaxial layer to form a trench;
forming a diffusion barrier layer conformally in the trench, wherein the diffusion barrier layer comprises a barrier oxide layer;
removing a portion of the diffusion barrier layer on a bottom surface of the trench;
forming a conductive feature in the trench, wherein the conductive feature has a protruding portion that is higher than the epitaxial layer; and
removing the mask structure.

### Claim 9 (depends on 8)

The method as claimed in claim 8, wherein a width of the protruding portion is greater than a width of the conductive feature in the trench.

### Claim 10 (depends on 8)

The method as claimed in claim 8, wherein the protruding portion covers a top surface of the diffusion barrier layer.

### Claim 11 (depends on 8)

The method as claimed in claim 8, wherein the mask structure comprises one or more than one dielectric layers.

### Claim 12 (depends on 11)

The method as claimed in claim 11, wherein the mask structure comprises a first oxide layer and a nitride layer formed on the first oxide layer.

### Claim 13 (depends on 12)

The method as claimed in claim 12, wherein the mask structure further comprises a second oxide layer formed on the nitride layer.

### Claim 14 (depends on 11)

The method as claimed in claim 11, wherein the mask structure comprises multiple dielectric layers, and removing the mask structure comprises:
removing a portion of the mask structure without removing a layer of the multiple dielectric layers which is closest to the epitaxial layer; and
after removing the portion of the mask structure, removing remaining of the mask structure.

### Claim 15 (depends on 8)

The method as claimed in claim 8, wherein the diffusion barrier layer comprises one or more than one dielectric barrier layers.

### Claim 16 (depends on 15)

The method as claimed in claim 15, wherein the diffusion barrier layer further comprises a barrier nitride layer formed on the barrier oxide layer.

### Claim 17 (depends on 8)

The method as claimed in claim 8, further comprising forming a drain region in the epitaxial layer, wherein the diffusion barrier layer contacts the drain region and separates the drain region from the conductive feature.

### Claim 18 (depends on 8)

The method as claimed in claim 8, wherein the conductive feature is formed between two laterally diffused metal oxide semiconductors (LDMOSs) and the conductive feature penetrates a common source region of the LDMOSs.