# US 10,770,391 B2 · Transistor with gate extension to limit second gate effect

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,770,391 B2
- Document ID: US10770391B2
- Status: Granted
- Kind: B2
- Application number: 15/936,907
- Filed: 2018-03-27
- Published: 2019-10-03
- Granted: 2020-09-08
- Earliest claimed: 2018-03-27
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Plamen Vassilev Kolev; Michael Andrew Stuber; Lee-Wen Chen
- Web page: https://patentgrep.com/patent/US10770391B2

## CPC

- H10W 20/423: {Shielding layers}
- H10D 30/637: {Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs}
- H10D 30/6715: {characterised by the doping profiles, e.g. having lightly-doped source or drain extensions}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 86/0214: {using temporary substrates}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 44/501: {Inductive arrangements (H10W44/20 takes precedence)}
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10W 44/248: {for antennas}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A transistor may include a semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region. The channel region may have a source interface and a drain interface, and may be bounded by edges extending from the source interface to the drain interface on two boundaries between a field-sensitive semiconductor material and an isolation material. The transistor may further include an insulator layer on the channel region. The transistor may further include a gate on the insulator layer. The gate may have extensions beyond edges of the channel region. The extensions may substantially exceed a minimum specified value.

## Claims

### Claim 1

A transistor, comprising:
a semiconductor layer comprising a source region, a drain region, and a channel region between the source region and the drain region, the channel region having a source interface, a drain interface, and bounded by edges of the channel region extending from the source interface to the drain interface, wherein the edges of the channel region are on two boundaries between a field-sensitive semiconductor material and an isolation material;
an insulator layer on the channel region;
a gate on the insulator layer, the gate disposed over the channel region and extending entirely between the source region and the drain region, the gate having extensions beyond the edges of the channel region, the extensions configured to protect the edges of the channel region from electrical fields generated from a handle wafer; and
a conductive shield over the gate extended beyond the edges of the channel region.

### Claim 2 (depends on 1)

The transistor of claim 1, further comprising:
a first inter-metal dielectric (IMD) layer on the gate; and
the conductive shield on the first inter-metal dielectric layer.

### Claim 3 (depends on 2)

The transistor of claim 2, in which the conductive shield comprises an opening.

### Claim 4 (depends on 2)

The transistor of claim 2, in which the conductive shield covers a transition from the gate to the source region across the channel region, and a transition from the gate to the drain region across the channel region.

### Claim 5 (depends on 1)

The transistor of claim 1, in which the transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET).

### Claim 6 (depends on 1)

The transistor of claim 1, in which the channel region has an opposite polarity to a polarity of the source region and the drain region.

### Claim 7 (depends on 1)

The transistor of claim 1, integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

### Claim 8 (depends on 1)

The transistor of claim 1, wherein the conductive shield is wider than the gate.

### Claim 9 (depends on 1)

The transistor of claim 1, wherein the conductive shield is longer than the gate.

### Claim 10 (depends on 1)

The transistor of claim 1, wherein the conductive shield is connected to the source region.

### Claim 11 (depends on 1)

The transistor of claim 1, wherein the conductive shield is wider than the handle wafer.

### Claim 12 (depends on 1)

The transistor of claim 1, wherein the channel region has a same polarity to a polarity of the source region and the drain region.

### Claim 13 (depends on 12)

The transistor of claim 12, wherein the channel region has lighter doping than the source region and the drain region.

### Claim 14

A transistor, comprising:
a semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region, the channel region having a source interface, a drain interface, and bounded by edges of the channel region extending from the source interface to the drain interface, wherein the edges of the channel region are on two boundaries between a field-sensitive semiconductor material and an isolation material;
an insulator layer on the channel region;
a gate on the insulator layer, the gate disposed over the channel region and extending entirely between the source region and the drain region, the gate having extensions beyond the edges of the channel region, the extensions configured to protect the edges of the channel region from electrical fields generated from a handle wafer; and
a shielding means over the gate to protect the edges of the channel region from the electrical fields generated from the handle wafer.

### Claim 15 (depends on 14)

The transistor of claim 14, further comprising an opening within the shielding means.

### Claim 16 (depends on 14)

The transistor of claim 14, integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.