# US 10,770,388 B2 · Transistor with recessed cross couple for gate contact over active region integration

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- Number: US 10,770,388 B2
- Document ID: US10770388B2
- Status: Granted
- Kind: B2
- Application number: 16/009,200
- Filed: 2018-06-15
- Published: 2019-12-19
- Granted: 2020-09-08
- Earliest claimed: 2018-06-15
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Ruilong Xie; Veeraraghavan S. Basker; Kangguo Cheng; Jia Zeng; Youngtag Woo; Mahender Kumar; Guillaume Bouche
- Web page: https://patentgrep.com/patent/US10770388B2

## CPC

- H10W 20/432: {comprising crossing interconnections}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 76/2043: {using an anti-reflective coating}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/0698: {Local interconnections}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10B 10/12: {comprising a MOSFET load element}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor structure includes a substrate having a first region and a second region, a first source/drain disposed on the substrate in the first region, an interlevel dielectric (ILD) disposed on the source/drain, and a first gate disposed on the substrate. The semiconductor structure further includes a first contact trench within the ILD extending to the first source/drain, a first trench contact within the first contact trench, and a first source/drain contact trench extending to the first trench contact. The semiconductor structure further includes a cross couple contact trench within the ILD, and a cross couple contact disposed in the cross couple contact trench in contact with the first gate and the first trench contact. The cross couple contact couples the first source/drain and the first gate.

## Claims

### Claim 1

An apparatus comprising:
a semiconductor structure including a substrate having a first region and a second region;
a first source/drain disposed on the substrate in the first region;
an interlevel dielectric (ILD) disposed on the source/drain;
a first gate disposed on the substrate;
a first spacer disposed between the first source/drain and the first gate;
a first contact trench within the ILD extending to the first source/drain;
a first trench contact within the first contact trench;
a first source/drain contact trench extending to the first trench contact;
a cross couple contact trench within the ILD; and
a cross couple contact disposed in the cross couple contact trench in contact with the first gate and the first trench contact, the cross couple contact coupling the first source/drain and the first gate such that the cross couple contact is substantially connected to a singular surface of the first source/drain.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising:
a first cap disposed on the first gate.

### Claim 3 (depends on 1)

The apparatus of claim 1, further comprising:
an ILD fill upon the semiconductor structure; and
a first metallization layer within the ILD fill of the first region, wherein the first metallization layer is electrically isolated from the cross couple contact.

### Claim 4 (depends on 1)

The apparatus of claim 1, further comprising:
a second source/drain disposed on the substrate in the second region;
a second contact trench within the ILD extending to the second source/drain; and
a second trench contact within the second contact trench such that the second trench contact is substantially connected to a singular surface of the second source/drain.

### Claim 5 (depends on 1)

The apparatus of claim 1, further comprising:
an anti-reflective coating material layer disposed over the semiconductor structure.

### Claim 6 (depends on 1)

The apparatus of claim 1, further comprising:
an ILD fill material disposed over the semiconductor structure.

### Claim 7 (depends on 1)

The apparatus of claim 1, further comprising:
a first metallization layer deposed within the ILD, wherein the first metallization layer is electrically isolated from the cross couple contact.

### Claim 8 (depends on 1)

The apparatus of claim 1, further comprising:
a second contact trench within the ILD extending to a second source/drain of the second region.

### Claim 9 (depends on 8)

The apparatus of claim 8, further comprising:
a second trench contact within the second contact trench.