# US 10,770,387 B2 · Integrated circuit package substrate

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- Number: US 10,770,387 B2
- Document ID: US10770387B2
- Status: Granted
- Kind: B2
- Application number: 16/381,889
- Filed: 2019-04-11
- Published: 2019-10-03
- Granted: 2020-09-08
- Earliest claimed: 2016-09-08
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Qinglei Zhang; Stefanie M. Lotz
- Web page: https://patentgrep.com/patent/US10770387B2

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- C23C 18/32: Coating with nickel, cobalt or mixtures thereof with phosphorus or boron (C23C18/50 takes precedence)
- C23C 18/42: Coating with noble metals
- H10P 14/46: using a liquid
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/66: Conductive materials thereof
- H10W 70/685: comprising multiple insulating layers
- H10W 70/69: Insulating materials thereof
- H10W 72/00: Interconnections or connectors in packages
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/072: {of bump connectors}
- H10W 72/07223: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.

## Claims

### Claim 1

A method for providing a package substrate, comprising:
providing one or more lands on a first side of the package substrate, the package substrate including a second side opposite the first side;
disposing one or more die bond pads on the second side, including providing the one or more die bond pads in a die interconnect region of the package substrate, wherein the die interconnect region comprises a silicon bridge;
depositing a first surface finish on at least one of the one or more lands; and
depositing a second surface finish on at least one of the die bond pads;
wherein the second surface finish has a different chemical composition than the first surface finish.

### Claim 2 (depends on 1)

The method of claim 1, wherein disposing the die bond pads includes disposing at least one die bond pad on the silicon bridge.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first surface finish is an outermost surface finish on the one or more lands and the second surface finish is an outermost surface finish on the one or more die bond pads.

### Claim 4 (depends on 1)

The method of claim 1, wherein the second surface finish is imidazole or an imidazole derivative.

### Claim 5 (depends on 1)

The method of claim 1, wherein the second surface finish is gold (Au).

### Claim 6 (depends on 1)

The method of claim 1, wherein the second surface finish is a combination of palladium (Pd) and gold (Au).

### Claim 7 (depends on 1)

The method of claim 1, wherein the second surface finish has a thickness of less than or equal to 500 nanometers.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first surface finish comprises nickel (Ni).

### Claim 9 (depends on 8)

The method of claim 8, wherein the first surface finish further comprises one or both of palladium (Pd) or gold (Au).

### Claim 10

A method for providing an assembly, comprising:
disposing a silicon bridge in a substrate of the assembly;
disposing a plurality of lands on a first side of the substrate;
providing a plurality of die bond pads, including disposing at least one die bond pad on the silicon bridge and disposing at least one other die bond pad on a second side of the substrate, the second side of the substrate opposite the first side;
depositing a first surface finish on at least one of the lands;
depositing a second surface finish on at least one of the die bond pads, wherein the second surface finish has a different chemical composition than the first surface finish;
extending a first set of interconnect structures between a first die of the assembly and the die bond pads; and
extending a second set of interconnect structures between a second die of the assembly and the die bond pads.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
disposing routing features in the silicon bridge, to electrically couple the first die and the second die.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
disposing routing features in the substrate, to electrically couple the first die and the second die.

### Claim 13 (depends on 10)

The method of claim 10, wherein the first surface finish is an outermost surface finish on the one or more lands and the second surface finish is an outermost surface finish on the one or more die bond pads.

### Claim 14 (depends on 10)

The method of claim 10, wherein the second surface finish is imidazole or an imidazole derivative.

### Claim 15 (depends on 10)

The method of claim 10, wherein the second surface finish is gold (Au).

### Claim 16 (depends on 10)

The method of claim 10, wherein the second surface finish is a combination of palladium (Pd) and gold (Au).

### Claim 17 (depends on 10)

The method of claim 10, wherein the second surface finish has a thickness of less than or equal to 500 nanometers.

### Claim 18 (depends on 10)

The method of claim 10, wherein the first surface finish comprises nickel (Ni).

### Claim 19 (depends on 18)

The method of claim 18, wherein the first surface finish further comprises one or both of palladium (Pd) or gold (Au).

### Claim 20 (depends on 10)

The method of claim 10, wherein the first and second dies comprise integrated circuits (IC).