# US 10,770,385 B2 · Connected plane stiffener within integrated circuit chip carrier

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- Number: US 10,770,385 B2
- Document ID: US10770385B2
- Status: Granted
- Kind: B2
- Application number: 16/046,653
- Filed: 2018-07-26
- Published: 2020-01-30
- Granted: 2020-09-08
- Earliest claimed: 2018-07-26
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Anson J. Call; Brian W. Quinlan; Krishna R. Tunga
- Web page: https://patentgrep.com/patent/US10770385B2

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 70/685: comprising multiple insulating layers
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/231: {characterised by their places of attachment or cooling paths}
- H10W 40/235: {attached to package parts}
- H10W 40/242: {comprising thermal conductors between chips and the and the arrangements for cooling, e.g. compliant heat-spreaders}
- H10W 40/251: {Organics}
- H10W 40/611: {Bolts or screws}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 76/15: Containers comprising an insulating or insulated base
- H10W 76/60: Seals
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier.

## Claims

### Claim 1

A method of fabricating an integrated circuit (IC) chip carrier comprising a lower surface, an upper surface, and a center, the method comprising:
forming a first plane fabrication layer upon a lower periphery layer, the lower periphery layer comprising the lower surface of the IC chip carrier;
forming one or more first planes within the first plane fabrication layer;
forming a plane separation layer upon the one or more first planes and upon the first plane fabrication layer;
forming a plurality of channel vias within the plane separation layer and upon the one or more first planes, each channel via comprising a width, a length greater than the width, and a width bisector that is coincident with the center of the IC chip carrier;
forming a second plane fabrication layer upon the plurality of channel vias and upon the plane separation layer;
forming one or more second planes within the second plane fabrication layer and upon the plurality of channel vias; and
forming an upper periphery layer upon the one or more second planes and upon the plane fabrication layer, the upper periphery layer comprising the upper surface of the IC chip carrier.

### Claim 2 (depends on 1)

The method of claim 1, wherein the one or more first planes and the one or more second planes resist bending moments internal to the IC chip carrier.

### Claim 3 (depends on 1)

The method of claim 1, wherein the plurality of channel vias resist shear forces internal to the IC chip carrier.

### Claim 4 (depends on 1)

The method of claim 1, wherein the one or more first planes distributes power potential within the IC chip carrier and wherein the one or more second planes distributes power potential within the IC chip carrier.

### Claim 5 (depends on 1)

The method of claim 1, wherein the one or more first planes distributes ground potential within the IC chip carrier and wherein the one or more second planes distributes ground potential within the IC chip carrier.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the one or more first planes within the first plane fabrication layer comprises:
forming one or more first plane trenches within the first plane fabrication layer; and
forming one first plane within each first plane trench.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the plurality of channel vias within the plane separation layer and upon the one or more first planes comprises:
forming a plurality of channel via trenches within the plane separation layer exposing a portion of an upper surface of the one or more first planes; and
forming one channel via within each channel via trench upon the exposed portion of the upper surface of the one or more first planes.

### Claim 8 (depends on 1)

The method of claim 1, wherein forming the one or more second planes within the second plane fabrication layer and upon the plurality of channel vias comprises:
forming one or more second trenches within the second plane fabrication layer exposing the plurality of channel vias; and
forming one second plane within each second plane trench and upon the plurality of channel vias.