# US 10,770,384 B2 · Printed circuit board having insulating metal oxide layer covering connection pad > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,384 B2 - Document ID: US10770384B2 - Status: Granted - Kind: B2 - Application number: 15/803,831 - Filed: 2017-11-05 - Published: 2018-08-30 - Granted: 2020-09-08 - Earliest claimed: 2017-02-24 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Soo-jae Park; Moon-gi Cho - Web page: https://patentgrep.com/patent/US10770384B2 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10P 72/74: {using temporarily an auxiliary support} - H10W 70/095: {of vias therein} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/635: {Through-vias} - H10W 70/66: Conductive materials thereof - H10W 70/69: Insulating materials thereof - H10W 70/695: Organic materials - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/685: comprising multiple insulating layers - H10W 72/075: {of bond wires} - H10W 72/07555: {changes in materials} - H10W 72/354: {comprising polymers} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/5522: {comprising gold [Au]} - H10W 72/5528: {Intermetallic compounds} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A printed circuit board (PCB) is provided as follows. A first connection pad and a second connection pad are disposed on a first surface and a second surface of the base substrate layer, respectively. The first connection pad and the second connection pad each includes a first metal. A first pad cover layer covers a top surface of the first connection pad and includes an insulating metal oxide having a second metal different from the first metal. ## Claims ### Claim 1 A printed circuit board (PCB) comprising: a base substrate layer; a first connection pad and a second connection pad disposed on a first surface and a second surface of the base substrate layer, respectively, wherein the first connection pad includes a top surface and a plurality of side surfaces extending from the top surface to the first surface of the base substrate layer, and wherein the first connection pad and the second connection pad each comprises a first metal; a first pad cover layer covering the top surface of the first connection pad and comprising an insulating metal oxide having a second metal different from the first metal; a first wire disposed on the first surface of the base substrate layer and located at a same level as the first connection pad with respect to the second surface of the base substrate layer, wherein the first wire comprises a same material as the first connection pad; a first wire cover layer covering a top surface of the first wire and comprising a same material as the first pad cover layer; and a first solder resist layer disposed on the first surface of the base substrate layer to cover entirely a top surface of the first wire cover layer without covering a portion of the first pad cover layer, wherein the first pad cover layer is absent from the plurality of side surfaces of the first connection pad. ### Claim 2 (depends on 1) The PCB of claim 1, wherein the first connection pad is embedded in the base substrate layer. ### Claim 3 (depends on 1) The PCB of claim 1, further comprising: a second pad cover layer covering a top surface of the second connection pad and comprising an insulating metal oxide having the second metal. ### Claim 4 (depends on 3) The PCB of claim 3, further comprising: a second wire disposed on the second surface of the base substrate layer to be located at a same level as the second connection pad with respect to the first surface of the base substrate layer, wherein the second wire comprises a same material as the second connection pad; a second wire cover layer covering a top surface of the second wire and comprising a same material as the second pad cover layer; and a second solder resist layer disposed on the second surface of the base substrate layer to cover entirely a top surface of the second wire cover layer without covering a portion of the second pad cover layer. ### Claim 5 (depends on 4) The PCB of claim 4, wherein the second connection pad protrudes from the second surface of the base substrate layer. ### Claim 6 (depends on 3) The PCB of claim 3, wherein a thickness of the second pad cover layer is greater than a thickness of the first pad cover layer, and wherein the thickness of the first pad cover layer is less than about 5.0 nm. ### Claim 7 A semiconductor package comprising: a base substrate layer; a first connection pad and a second connection pad disposed on a first surface and a second surface of the base substrate layer, respectively, wherein the first connection pad and the second connection pad each comprises a first metal and wherein the first connection pad includes a top surface and a plurality of side surfaces extending from the top surface to the first surface of the base substrate layer; a first pad cover layer covering the top surface of the first connection pad and comprising an insulating metal oxide having a second metal different from the first metal, wherein the first pad cover layer is absent from the plurality of side surfaces of the first connection pad; a semiconductor chip comprising a chip pad; and a bonding wire comprising a first end connected to the chip pad and a second end connected to the first connection pad through the first pad cover layer, wherein the bonding wire comprises a third metal different from the first metal; and a first intermetallic compound arranged between the second end of the bonding wire and the first connection pad, wherein the first intermetallic compound is a compound of the first metal and the third metal; and first fragments arranged at an interface between the second end of the bonding wire and the first intermetallic compound, wherein the first fragments comprise a same material as the first pad cover layer. ### Claim 8 (depends on 7) The semiconductor package of claim 7, further comprising: a first wire disposed on the first surface of the base substrate layer and located at a same level as the first connection pad with respect to the second surface of the base substrate layer, wherein the first wire comprises a same material as the first connection pad; a wire cover layer covering entirely a top surface of the first wire and comprising a same material as the first pad cover layer; and a first solder resist layer disposed on the first surface of the base substrate layer to cover entirely a top surface of the wire cover layer without covering a portion of the first pad cover layer. ### Claim 9 (depends on 7) The semiconductor package of claim 7, further comprising: a solder joint attached onto the second connection pad and comprising a fourth metal; a second intermetallic compound arranged between the second connection pad and the solder joint, wherein the second intermetallic compound is a compound of the first metal and the fourth metal; and second fragments arranged at an interface between the solder joint and the second intermetallic compound and comprising an insulating metal oxide having the second metal. ### Claim 10 (depends on 9) The semiconductor package of claim 9, further comprising: a second pad cover layer covering a portion of the second connection pad and comprising an insulating metal oxide having the second metal. ### Claim 11 (depends on 10) The semiconductor package of claim 10, further comprising: a second solder resist layer disposed on the second surface of the base substrate layer to cover a top surface of the second pad cover layer. ### Claim 12 (depends on 9) The semiconductor package of claim 9, further comprising: a via wire penetrating the base substrate layer, wherein the via wire connects electrically the first connection pad to the second connection pad, and wherein the second fragments are arranged at a portion of the interface between the solder joint and the second intermetallic compound that does not overlap the via wire in a vertical direction and are not arranged at a portion of the interface that overlaps the via wire in the vertical direction. ### Claim 13 (depends on 7) The semiconductor package of claim 7, wherein the bonding wire penetrates the first pad cover layer to be in contact with the first connection pad. ### Claim 14 A semiconductor package comprising: a printed circuit board (PCB) comprising: a base substrate layer, a first connection pad and a second connection pad disposed on a first surface and a second surface of the base substrate layer, respectively, wherein the first connection pad includes a top surface and a plurality of side surfaces extending from the top surface to the first surface of the base substrate layer, and a first pad cover layer covering the top surface of the first connection pad, wherein the first pad cover layer is absent from the plurality of side surfaces of the first connection pad; and a semiconductor chip comprising a chip pad; a bonding wire comprising a first end connected to the chip pad and a second end connected to the first connection pad through the first pad cover layer, wherein the first pad cover layer has a thickness less than about 5.0 nm; a solder joint attached onto the second connection pad; a first intermetallic compound arranged between the second end of the bonding wire and the first connection pad; and fragments arranged at an interface between the second end of the bonding wire and the first intermetallic compound, wherein the fragments comprise a same material as the first pad cover layer. ### Claim 15 (depends on 14) The semiconductor package of claim 14, wherein the first connection pad comprises copper, and wherein the first pad cover layer comprises aluminum oxide. ### Claim 16 (depends on 14) The semiconductor package of claim 14, further comprising a second intermetallic compound arranged between the second connection pad and the solder joint. ### Claim 17 (depends on 14) The semiconductor package of claim 14, wherein the first connection pad is non-overlapped with the second connection pad. ### Claim 18 (depends on 17) The semiconductor package of claim 17, further comprising: a second pad cover layer covering a portion of a top surface of the second connection pad; and a solder resist layer covering the second pad cover layer and the top surface of the second connection pad, wherein the second pad cover layer is disposed between the solder resist layer and the second connection pad.